ECE 551 -- Designing Application-Specific Integrated Circuits

ECE 551 (Section# 001). Tues/Thurs 12:40 p.m. - 1:55 p.m. in 510 Ferris Hall

Don Bouldin, Ph.D.
Prof. of Electrical and Computer Engineering
419 Ferris Hall
1508 Middle Drive
University of Tennessee
Knoxville, TN 37996-2100
TEL: (VOL)-974-5444
FAX: (VOL)-974-5483
Email: dbouldin@utk.edu
http://www.ece.utk.edu/
http://www.eecs.utk.edu/faculty/bouldin
http://vlsi1.engr.utk.edu/ece/bouldin_courses/551/overview.html

FPGA & ASIC Synthesis

This project-oriented course will present an overview of the design of field-programmable gate arrays (FPGAs)
and application-specific integrated circuits (ASICs). Each pair of students will capture a design using a
hardware description language (VHDL) and then use synthesis and automatic placement and routing software
to implement the design using multiple technologies (Altera and Xilinx). Engineering workstations (SPARCs) will be used extensively.

Goals of ECE 551:

To present an overview of FPGAs and ASICs that are suitable for tasks which cannot be executed
efficiently by a general-purpose microprocessor.

To illustrate capturing a design in a technology-independent means using a mix of levels (behavior and structure)
and then to map the synthesized result into several technologies which can be compared.

To provide an in-depth project using FPGAs that will involve architectural tradeoffs and simulation.

To reinforce the lectures and discussions with experience using computer-aided design tools.

To develop human communication skills via a team project requiring both written and oral reports.

What's New ?

Accessing a Remote Host

Lab Equipment

Our Printed Text for $79 (optional)

Our Text On-Line for Free

Syllabus

Students

Course Overview (pdf file)

Overview Slides (color pdf)

Overview Slides (handout b/w pdf)

Synthesizing Microelectronic Systems (197 KByte pdf)

Homework_1 - LOGIN, EMAIL and WEB PAGE

Homework 2 -- Using ModelSim

Homework 3 -- Using the Spartan3 Demo Board

Homework 4 -- Animating Logic Simulations

Homework 5 -- Graphics <---> HDL

Homework_6 -- Using Design Flow Scripts for Flex and Virtex

Homework Status

Projects

Project Checkoff Appts

Final Exam

VHDL Tutorial Examples

Previously Tested VHDL

Previous 551 Projects

Previous 552 Projects

OpenCores

RESTRICTED WEBSITE

dbouldin@utk.edu