Implementing a Team Project

D. Bouldin -- 1/29/03

Groups for Spring 2007

Team Design Principles

Refresher--ModelSim, Synthesis, Virtex FPGA (551/hw6)

Part A: Stand-alone Development and Testing
Using the specifications presented during our class discussions, compose the VHDL and test-bench for a blackjack player. Incorporate your own unique strategy with the overall goal of achieving the highest rank among all players. The rank is determined by adding the number of hands played with the number of chips remaining (if any) at the end of the game.

Perform pre-synthesis simulation, synthesis, place/route, and post-layout simulation targeting the Virtex1000e.

Capture the pre-synthesis simulation waveform, the post-layout simulation waveform and the layout. List the number of slices used.

Part B: Integrate your player into the full game environment.
Record your rank for several games. You may revise your design and replay as desired.

Link your results to your restricted webpage.

Update /usr/cad/public_html/552hw_status.html