Written by F. Karakaya and D. Bouldin on 2/17/02
Revised by D. Bouldin on 2/6/06
The objective of this tutorial is to learn how to use Synopsys DesignWare components.
The circuit to be implemented combines three components into a single larger design:
(1) an adder, (2) a subtractor, and (3) a comparator. A schematic is shown below.
The instructions for this circuit produce different results:
VHDL files for the three components are given below:
DW01_cmp2_inst.vhdFirst, copy the VHDL files and a ModelSim script to your homework directory:
cp /usr/cad/course/552-hw4.tar .
tar -xvf 552-hw4.tar
cd designware
generate_hw4_for 4
A script called generate_hw4_for has been written to
automate the implementation for any desired bit-width by
passing an argument for the number of bits to a PERL
script called new_width
which alters a VHDL template to produce a new VHDL file with the desired number of bits.
To generate a 4-bit version, just type:
generate_hw4_for 4
cd modelsim
pre-synth_4
Note that no testbench has been supplied for you so you have to compose your own.
You can do that manually or by following the example 552-hw3 or this one:
/usr/cad/course/designware/dotproduct/vhdl/SourceTb.vhd
Capture the simulation waveform.
Now, generate an 8-bit version:
cd ..
generate_hw4_for 8
cd modelsim
pre-synth_8
Alter your testbench and caputure the simulation waveform.
Link your results to your restricted webpage.
Update /usr/cad/public_html/552hw_status.html
ANOTHER HIERARCHICAL DESIGNWARE EXAMPLE:
Complex Multiplier
(Re1+jIm1)*(Re2+jIm2)
