ECE 552 -- PROJECTS
D. Bouldin -- 3/05/07
Spring 2007:
Tasks:
01. Write the macro specifications (like hw1).
02. Determine the correct results
(e.g. write fixed-point C or Matlab routine (like hw5);
optional: do for 4-bits then 16).
03. Write the VHDL for the parametrized, hierarchical macro (like hw4).
04. Write the functional testbench in VHDL.
05. Perform pre-synthesis simulation using ModelSim with near 100% coverage and capture waveforms.
06. Synthesize for Xilinx VirtexIIPro (like hw2).
07. Perform place and route and capture layout.
08. Implement on the XUP board.
09. Synthesize for TSMC-0.18 WITH ATPG and Fault Grading (like hw3).
10. Perform place and route using Cadence and capture layout.
11. Prepare presentation and report documenting the results.
Schedule:
ASAP: Email "bouldin" to reserve a topic and a team color.
03/22/Thu: Post your proposal on website by noon.
04/03/Tue - 04/05/Thu: Give oral PPT presentation in class.
04/23/Tue - 04/25/Thu: Give final oral PPT presentation in class.
04/26/Thu: Post final report on website by noon.
Groundrules:
Each project should require partitioning as a team,
then individual implementations and then integration of the parts.
We want to use the FPGA to implement parallel, pipelined operations
and let the CPU handle data movement.
We want to verify FPGA results versus either C or MatLab implementations.
It is not okay to reuse high percentage of vhdl blocks from elsewhere.
All reporting can consist of a
PPT
file with extensive notes.
Teams:
Team Orange: bjohnso5-bsharp3 (#5); rbolt-muppala (#6) -- Comparison of Edge Detectors
Team Red: scaylor - vmahoney (#1); rchannap - cward19 (#2) -- Spatial Transformations
Team Silver: gkim2 - dyang7 (#3); zning -kyang (#4) -- Image Zooming
Team Blue: pmruetus- pparla (#8); dpatloll - asulakhe (#7) -- Image Proc. Toolbox
(contrast enhancement, deblurring, smoothing, neg-to-pos)
Spring 2006:
Team-Teal: Image Morphing with Skeleton Transform
ajain4, ayarlaga, lzhang12, msharafa
Team-Radioactive Green: Color Slicing
aalbrig1, ccarrol2, dbudik, ldavis42
Team-Black: Image Filtering in a Noisy Environment
bhatch, jhatche2, ksundar1
Team-Orange: Image Resizing, Recoloring and Reshaping
czhang5, jlee57, ybi1, zliu4
Team-Blue: Multiple Image Enhancment Techniques
djayaram, jkruttiv, nkarnam, vvenkata
Spring 2005:
Team-Onyx: Audio Processing
jbritton, sbunch, robertg, dziemian
Team-Red: Handwritten Digit Recognition
gabone, rchai, ntroy, vprasad
Team-Amber: Voice Recognition
gliang, csu, bthurmon, weathers
Team-Purple: Image Padding, Shearing and Filtering
ecardwel, ndennis, darren, ckiger
Team-Midnight Blue: Cell Detection Using Image Segmentation
cbeall1, keharvey, mprice5
Team-Green: Digital Watermarking using Wavelet Transformation
vgirinat, culagana, mzhang2
Team-Blue: Spatial Transformations of Images
ishaik, ksubram1, tmarwah, pchimaku
Spring 2004:
Team Aqua: Edge Operators
bnelson3, sfields1, bdalton5, fkuhlman
Team Zero: K-means Clustering
gilbert, jwhite25, jpendlet, turnmire
Team White: LZW Compression
ckhor, nmichou, nnambiar, ooyeyele
Scott Fields will get the Orange team project from spr03 working
and show others how to use it.
We will use the pilchard machines during spr04.
-----------------------------
Voice Box
Image Tool Box (K-means; Rotation; Cell Detection)
Morphing
Morphing (zip)
Data Compression
Compression Research
Research Projects at Northeastern Univ.
LZW
Fort Carson Images
Lenna Image
-----------------------------
DSP Guide
Numerical Recipies
VSIPL code is on-line at:
/usr/cad/course/vsipl/tvcp
tasp_core_plus_book (pdf)
Spring 2003:
ORANGE
(baugher jjackson mccollum stinson): Image Processor Results
BLUE
(gabi wala kramani madhan): Discrete Cosine Transform
WHITE
(wjiang xiang suresh wakeland): Huffman Decoding of MPEG Audio
Spring 2002:
Team Meetings on 2/21/Thu, 2/28/Thu and 3/7/Thu
Class Meetings and Team Oral Reports on 2/26/Tue and 3/5/Tue.
sampath/vbhaskar/mdorai/sirisha
DCT: Discrete Cosine Transform (pdf)
VHDL and C code in
/usr/cad/acs/release1.2/microk~1/src
swann/scterry/clanden/yhe
Decimated FIR Filter
Cascaded IIR Filter
See VSIPL (pdf); begin at page 627
Also, see: Xilinx IP
Decimating Cascaded Integrated Comb Filter
mchintha, kpatel5, smerchan, nraghura
See VSIPL (pdf); begin at page 581
ntiwari, rishi, bobrek, jbritten
See VSIPL (pdf); begin at page 651
General Matrix Product
General Matrix Sum
Matrix Vector Product
Matrix Transpose
Vector Dot Product
balash/sdevalap
See VSIPL (pdf); begin at page 619
Blackman Window
Chebyshev Window
Hamming Window
Kaiser Window
jrudisil, hdu1, yhl
Rounders (pdf)
Fixed Rounder
Configurable Rounder 4/8/16
Output Gain Section