A.
I had some trouble initially with pins while doing Homework 5. I had to add certain pins (for example for input and output) removing the pins which were already there. Sometimes, if I do not add pins, then LVS would mismatch. However, when I added Abstract, it would complain saying that there is already pin a there so I solved that by removing the already present pin and adding my own.
B.
When we add VDD and GND pins, we should give access direction for them as "Left and Right". When we click on "create ---> pins" a box will pop-up where we usually give "pin's name ". At the bottom there would be something like "Access direction" We need to disable everthing except "Left and right" for vdd and gnd and "Top and Bottom" for Input and Output. This solved that problem.
C.
I think that metal-2 pins should be at the vertical cross section
(vertical line of the grid should pass through the center of metal-2 pin
as in the case of Input and Output),
Metal-1 pins should be at the Horizontal cross section
(Horizontal line of grid should pass through the center of the metal-1 pin,
in the case of VDD and GND) and when we have both metal-1 and metal-2,
its center should be at the cross section.
DWB will double-check the following in Fall 04.
Metal-2 rules dictate the horizontal spacing of 1.6u or 8-lambda
while metal-1 rules dictate the vertical spacing of 2.0u or 10-lambda.
Using a grid permits the cell boundaries to overlap horizontally by 4.8u (16-lambda).
The vertical overlap of the cell boundaries is 4.8u (vdd) or 2.4u (gnd):
Note how the individual cell grids overlap horizontally by (4-lambda) and vertically by (5-lambda):
5. Select "Verify-->DRC" and iterate until there are no errors.
6. Save the layout and then extract it.
Update: 1. You can skip steps 7-11 which ask you to produce the abstract view. 2. The cells you generate will not be used by others this semester.7. Also, produce the abstract view of the layout: "Tools-->Abstract"
8. "Abstract-->Set cellview properties-->rectangle"
9. "Abstract-->Auto Boundary":
Draw the Auto boundary manually (using "pr boundary dg") over the edge of the Grid.
10. "Abstract-->Abgen"
Note: abgen.rul is located at /sw/CDS/local/lib/NCSU_TechLib_ami06
11. "Library Manager-->Open abstract" view to see NAND3_abs
12. Perform simulation using Spectre.
13. Install each standard cell in the library by generating the LEF (layout exchange format).
14. Store your new cells in the two new libraries:
UT-MATCH-AMI04 and UT-SAME-AMI04
Then, other students can use your cells when doing Homework 6 and their projects.
Under the Library Manager window, select "edit -> library path"
or add the library path to the file "cds.lib" in the working directory
and restart icfb.
Thanks to Ashwin Balash for adapting these instructions from information provided by Miss. State Univ. and Dr. Chandra Tan at UTK.
From balash@vlsi1.engr.utk.edu Mon Oct 28 16:01:55 2002
Subject: Suggestion in LEF generation
In slide #36 , I should have given the name to be given as "core".
(it is better to give in small c, because if we give the name as "Core"
the lef file will have both "core" and "Core" which might be misleading).
In the last slide #49, I should have asked to change the Size from "2.4
and 18.000" to "2.4 and 24.000". While you open the LEF file for the first
time and if you see the following (given below) there is no need to change
the value to 24.000.
When we scroll down in the LEF file we should see the following
"SITE core
CLASS CORE ;
SYMMETRY Y ;
SIZE 2.400 BY 24.000 ;
END core
"
Where SITE core and END core infers that we have given the name as "core"
An excellent set of solutions for INV may be viewed here.
Solution provided by Nazmul Islam:
Link your results to your web home page.
Update /usr/cad/public_html/651hw_status.html