Homework_6 -- Implementing a Soft-Macro

General Procedure

   
As of 10/05/07, generation of the Verilog-XL netlist is not working 
so skip to the Implementation section.

1. Invoke icfb and use Composer to draw a schematic which uses multiple leaf_cells.

2. Generate the net-list for Verilog-XL.

3. Edit the Verilog-XL net-list to make the I/O ports be in the
   same order as defined in osu05_stdcells.v 

4. Perform simulation using Verilog-XL.

5. Generate the net-list for Spectre.

6. Simulate pre-layout using Spectre.

7. Use SOC_Encounter to perform placement and routing automatically and to produce the DEF file.

8. Use Virtuoso to read in the DEF file, add pins for gnd! and vdd!
(Notes: Skip to page 4 and in the command window, perform "Import-def".
(On page 7, replace "Replace-All" with "Apply, then Replace-All".)

9. Perform DRC.

10. Extract the cell and compare LVS.

11. Simulate post-layout using Spectre.


Implementations

mkdir 651-hw6

cp /usr/cad/course/651-hw6.tar 651-hw6

cd 651-hw6

tar -xvf 651-hw6.tar

cd 651-hw6

ls

You should have the following files:

osu05_stdcells.stacks.lef*
osu05_stdcells.tlf*
osu05_stdcells.v*
parta.v
parta_script*
partb.v
partb_script*
partc.v
partc_script*


Part A (NAND):

Note in parta_script:   floorPlan -r 0.5 1.0 10 10 10 10

cadenceSOC_tools; encounter

encounter 1> source parta_script

capture the layout which in my case is 30u high and 36u wide:



encounter 2> exit



Part B (one row 4-bit ADDER like hw4-case 2):

Note in partb_script:   floorPlan -r 0.5 1.0 10 10 10 10

cadenceSOC_tools; encounter

encounter 1> source partb_script

capture the layout which in my case is 30u high and 172.8u wide:





encounter 2> exit


Part C (square 4-bit ADDER like hw4-case 2 using two rows):

Note in partc_script:   floorPlan -r 0.8 0.95 10 10 10 10

cadenceSOC_tools; encounter

encounter 1> source partc_script

capture the layout which in my case is 60u high and 88.8u wide:



encounter 2> exit