Tues/Thurs--2:10-3:25 p.m. in 510 FH
| Session | Date | Topic |
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| 01 | 08/23/Thu | Introduction to VLSI Systems |
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| 02 | 08/28/Tue | CMOS Modeling (Harris#3); HW1 |
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| 03 | 08/30/Thu | Basic Logic Circuits |
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| 04 | 09/04/Tue | Custom Layout; Describe HW2 |
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| 05 | 09/06/Thu | Leaf Cell Design Flow |
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| 06 | 09/11/Tue | Pre-Layout & Post-Layout Simulation (Harris#4) |
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| 07 | 09/13/Thu | Rules for Datapath Cells; Describe HW3 |
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| 08 | 09/18/Tue | Loading and Wiring Delays (Harris#5-6); HW4 |
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| 09 | 09/20/Thu | Rules for Standard-height Cells; HW5 |
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| 10 | 09/25/Tue | Placement and Routing |
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| 11 | 09/27/Thu | Soft Macros; Describe HW6 |
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| 12 | 10/02/Tue | Big Leafcells |
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| 13 | 10/04/Thu | Psuedo-NMOS; Domino Logic (Harris#9) |
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| 14 | 10/09/Tue | No Class (miss# 1) |
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| -- | 10/11/Thu | No Class (Fall Break) |
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| 15 | 10/16/Tue | Leafcell Generators; Describe HW8 |
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| 16 | 10/18/Thu | Latches and Flip-Flops (Harris#10) |
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| 17 | 10/23/Tue | No Class (miss# 2) |
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| 18 | 10/25/Thu | Analog Design (Prof. Blalock); HW7 |
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| 19 | 10/30/Tue | Clock Skew (Weste#7) |
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| 20 | 11/01/Thu | Clock Tree Synthesis; Describe HW9 |
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| 21 | 11/06/Tue | Latchup and ESD (Harris#20) |
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| 22 | 11/08/Thu | I/O Pads |
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| 23 | 11/13/Tue | Using Nanosim; HW10 |
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| 24 | 11/15/Thu | Signal Integrity |
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| 25 | 11/20/Tue | No Class (miss# 3) |
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| -- | 11/22/Thu | No Class (Thanksgiving) |
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| 26 | 11/27/Tue | Static Timing Analysis; HW11 |
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| 27 | 11/29/Thu | System-on-Chip Design |
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| 28 | 12/04/Tue | Physical Synthesis |
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| 29 | 12/05/Wed | All Homework Due |
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| 30a | 12/05/Wed | Final Exam (9 a.m. - 11 a.m. -- optional) |
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| 30b | 12/10/Mon | Final Exam (2:45-4:45 p.m. -- reqd) |
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