ECE 652 -- Computer-Aided Design of VLSI Systems II

Section# 001 -- Spring 2007
Tues/Thurs 2:10 p.m. - 3:25 p.m. in 511 Ferris Hall

Don Bouldin, Ph.D.
Prof. of Electrical & Computer Engineering
419 Ferris Hall
1508 Middle Drive
University of Tennessee
Knoxville, TN 37996-2100
TEL: (VOL)-974-5444
FAX: (VOL)-974-5483
Email: dbouldin@utk.edu
http://www.ece.utk.edu/
http://www.ece.utk.edu/bios/Faculty/Bouldin.html
http://www-ece.engr.utk.edu/ece/bouldin_courses/652/overview.html

Overview:
We will perform system-on-chip design as a single large team.
We will use the ModelSim simulator, Synopsys physical synthesis (psyn)
Synopsys NanoSim targeting a 180-nm (and possibly a 90-nm) CMOS process
that is available via MOSIS. The system-on-chip contains:
Leon CPU, AMBA buses, other DesignWare, filtering and encryption.

We will explore power-delay-area solutions at the RTL synthesis level
and explore physical design issues including floorplanning and clocktree synthesis.
We will also discuss higher-level tools including: platform-express, seamless-cve,
systemc, cocentric, and transaction-level modeling.

ECE 651

ECE 552

Goals of ECE 652:

To understand the principles of hierarchical design of digital VLSI systems.

To utilize CAD tools to explore design alternatives and enhance productivity.

To experience the above goals through practical projects implementing integrated circuits.

What's New ?

Syllabus

Students

Homework Status

RESTRICTED WEBSITE

dbouldin@utk.edu