how-to-get-a-paper-accepted.doc
Guides for Writing and Presentations and References
Mosterman, P., Rucinski, A. and D. Bouldin, ``A Peer Reviewed Online Computational Modeling Framework '' (0.1 MByte pdf) , Proceedings of the American Society for Engineering Education Annual Conference (ASEE), Pittsburgh, PA,(accepted but was left out of the proceedings) Jun. 22-25, 2008.
Newport, D. and D. Bouldin, ``Using Configurable Computing Systems '' (0.1 MByte pdf) , Computer Engineering Handbook, Second Edition, Edited by Vojin Oklobdzija, CRC Press, pp. 21-18 thru 21-24 (2007).
Sharafat, M., ``FPGA-based Image Analysis System for Cotton Classing'' (4.4 MByte pdf file) , M.S. Thesis, University of Tennessee, Dec. 2007.
Bouldin, D., Rucinski, A. and T. Kochanski, ``Paradigm Shifts in the Design of Microelectronic Systems,'' (3.3 MByte restricted pdf file) in Pursuit of the 21st Century Golden Key, B. Sheu, C.-Y. Wu and M.-D. Ker, (Editors), ISBN: 978986829970, Hsin-Chu, Taiwan: National Chiao Tung University Press, 2007, pp. 4-8 thru 4-187.
Bouldin, D., Rucinski, A. and T. Kochanski, ``A Roadmap Towards Microelectronics Education in the Global Era,'' (0.2 MByte pdf file) Proceedings of the Fifth IEEE East-West Design and Test Symposium (EWDTS), Yerevan, Armenia, pp. 192-195, Sep. 8-10, 2007.
Yelagondanahalli, V., ``Simulink to Silicon,'' (8 MByte pdf file) , M.S. 501 Project, University of Tennessee, Aug. 2007.
Sundaramurthy, K., ``ATPG and Scan Chain Diagnostics for Failure Analysis of Integrated Circuits,'' (2 MByte pdf file) , M.S. 501 Project, University of Tennessee, Aug. 2007.
Bouldin, D. and P. Chimakurthy, ``Experiences Teaching Physical Synthesis of FPGAs and ASICs'' (0.3 MByte pdf file),(Poster), Proceedings of the Microelectronic Systems Education Conference (MSE), San Diego, CA, pp. 79-80, Jun. 3-4, 2007.
Liang, G. ``Optimization of Digital Filter Design Using Hardware Accelerated Simulation'' (2.7 MByte pdf file) , M.S. Thesis, University of Tennessee, May, 2007.
Girinathan, V. ``Automation for Hardware Acceleration of Post-Layout Simulation of Integrated Circuits'' (1.1 MByte pdf file) , M.S. 501 Project, University of Tennessee, Dec. 2006.
Du, Hongtao, `` Efficient Image Processing in Resource-constrained Visual Sensor Networks '' (4.3 MByte pdf file) , Ph.D. Dissertation, University of Tennessee, Dec. 2006.
Jain, A. ``FPGA-Based Image Processing'' (1.1 MByte pdf file) , M.S. 501 Project, University of Tennessee, Dec. 2006.
Chimakurthy, P., ``Using Physical Compilation to Implement a SoC Platform'', (6.4 MByte pdf file) , M.S. Thesis, University of Tennessee, Dec., 2006.
Carroll, N. ``Source Code Revision Control'' (0.2 MByte pdf file) , M.S. 501 Project, University of Tennessee, Dec. 2006.
Bouldin, D., ``Synthesis of FPGAs and Testable ASICs '' (0.2 MByte pdf file) , Design of Systems on a Chip , Edited by R. Reis, M. Lubaszewski and J. Jess, ISBN: 0-387-32499-2 Chapter 10, pp. 211-221, Springer (2006).
Bouldin, D., ``VLSI Designer's Interface'' (0.2 MByte pdf file) , IEEE Circuits & Devices Magazine, vol. 22, nr. 6, pp. 3-5, Nov., 2006.
Bouldin, D., ``VLSI Designer's Interface'' (0.2 MByte pdf file) , IEEE Circuits & Devices Magazine, vol. 22, nr. 5, pp. 3-6, Sep., 2006.
Marwah, T., ``System-on-Chip Design and Test with Embedded Debug Capabilities'' (2.1 MByte pdf file) , M.S. Thesis, University of Tennessee, August, 2006.
Turnmire, J., ``Automated Design Space Exploration for Digital Hardware'' (1.4 MByte pdf file) , M.S. Thesis, University of Tennessee, August, 2006.
Mallette, C., ``High Performance Computer Operating Systems: Windows vs. Linux'' (2.1 MByte pdf file) , M.S. 501 Project, University of Tennessee, Aug. 2006.
Dennis, N., ``Power Spectral Density Estimation on an FPGA'' (4.6 MByte pdf file) , M.S. 501 Project, University of Tennessee, Aug. 2006.
Bouldin, D., ``VLSI Designer's Interface'' (0.2 MByte pdf file) , IEEE Circuits & Devices Magazine, vol. 22, nr. 4, pp. 8-9, Jul., 2006.
Bouldin, D., ``VLSI Designer's Interface'' (0.2 MByte pdf file) , IEEE Circuits & Devices Magazine, vol. 22, nr. 3, pp. 4-5, May, 2006.
Bouldin, D., ``Enhancing Electronic Systems Using Reconfigurable Hardware '' (2.6 MByte pdf file) , IEEE Circuits & Devices Magazine, , vol. 22, no. 3, pp. 32-36 (May 2006).
Stinson,B., ``Design and Test of an Event Detector and Locator for the ReflectoActive Seals System'' (1.8 MByte pdf file) , M.S. Thesis, University of Tennessee, May, 2006.
Du, H., Qi, H. and D. Bouldin, ``An Application-Oriented Virtual Microsensor Integration Platform'' (0.3 MByte pdf file) , Proceedings of the IEEE International Conference on Networking, Sensing and Control (ICNSC), pp. 874-879, Fort Lauderdale, FL, Apr. 23-25, 2006.
Bouldin, D., ``VLSI Designer's Interface'' (0.2 MByte pdf file) , IEEE Circuits & Devices Magazine, vol. 22, nr. 2, pp. 6-7, Mar., 2006.
Bouldin, D., ``VLSI Designer's Interface'' (0.2 MByte pdf file) , IEEE Circuits & Devices Magazine, vol. 22, nr. 1, pp. 4-5, Jan., 2006.
Khor, C., ``Tutorials for the Xilinx XUP Board'' (8.5 MByte ppt file) , M.S. 501 Project, University of Tennessee, Dec. 2005.
Chereches, G., ``Design and Verification of a Reusable Self-Reconfigurable Gate Array Architecture'' (7.2 MByte pdf file) , M.S. Thesis, University of Tennessee, Dec. 2005.
Fields, S., ``Hardware Design and Implementation of Role-Based Cryptography'' (0.6 MByte pdf file) , M.S. Thesis, University of Tennessee, Dec. 2005.
Jiang, W., ``Enhancing System-on-Chip Verification Using Embedded Test Structures'' (1.7 MByte pdf file) , M.S. Thesis, University of Tennessee, Dec. 2005.
Bouldin, D., ``VLSI Designer's Interface'' (0.4 MByte pdf file) , IEEE Circuits & Devices Magazine, vol. 21, nr. 6, pp. 3-4, Nov., 2005.
Bouldin, D., ``VLSI Designer's Interface'' (0.4 MByte pdf file) , IEEE Circuits & Devices Magazine, vol. 21, nr. 5, pp. 3-6, Sep., 2005.
Bouldin, D. ``Keynote: Emerging Trends in Circuits and Systems'' (1 MByte pdf file) , Proceedings of the Midwest Symposium on Circuits and Systems (MWSCAS), Cincinnati, OH, Aug. 7-10, 2005.
Fields, S. and D. Bouldin, ``Cryptographic Key Protection Module in Hardware for the Need2Know System'' (0.2 MByte pdf file) , Proceedings of the Midwest Symposium on Circuits and Systems (MWSCAS), Cincinnati, OH, Aug. 7-10, 2005, pp. 814-817.
Jiang, W., T. Marwah and D. Bouldin, ``Enhancing Reliability and Flexibility of a System-on-Chip Using Reconfigurable Logic'' (0.2 MByte pdf file) , Proceedings of the Midwest Symposium on Circuits and Systems (MWSCAS), Cincinnati, OH, Aug. 7-10, 2005, pp. 879-882.
Wala, M. and D. Bouldin, ``Integrating and Verifying Intellectual Property Blocks using Platform Express and ModelSim'' (0.4 MByte pdf file) , Proceedings of the Midwest Symposium on Circuits and Systems (MWSCAS), Cincinnati, OH, Aug. 7-10, 2005, pp. 758-761.
Bouldin, D., ``VLSI Designer's Interface'' (0.4 MByte pdf file) , IEEE Circuits & Devices Magazine, vol. 21, nr. 4, pp. 3-4, Jul., 2005.
Bouldin, D. ``Enabling Killer Applications of Reconfigurable Systems'' (3.5 MByte pdf file) , Proceedings of the Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, NV, Jun. 27, 2005.
Merchant, S., Peterson, G. and D. Bouldin: ``Improving Embedded Systems Education: Laboratory Enhancements Using Programmable Systems on Chip'', (0.1 MByte pdf file) , Proceedings of the Microelectronic Systems Education Conference (MSE), Anaheim, CA, pp. 5-6, Jun. 12-13, 2005.
Bouldin, D., ``VLSI Designer's Interface'' (0.4 MByte pdf file) , IEEE Circuits & Devices Magazine, vol. 21, nr. 3, pp. 4-5, May, 2005.
Wala, M., ``Using Platform Express for System-on-Chip Design'' (3.6 MByte pdf file) , M.S. Thesis, University of Tennessee, May 2005.
Bouldin, D., ``VLSI Designer's Interface'' (0.4 MByte pdf file) , IEEE Circuits & Devices Magazine, vol. 21, nr. 2, pp. 3-4, Mar., 2005.
Bouldin, D., ``VLSI Designer's Interface'' (0.4 MByte pdf file) , IEEE Circuits & Devices Magazine, vol. 21, nr. 1, pp. 3, 37 Jan., 2005.
Polisetty, S., ``Hardware Acceleration of the Embedded Zerotree Wavelet Algorithm'' (5.3 MByte pdf file) , M.S. Thesis, University of Tennessee, December 2004.
Bouldin, D., ``VLSI Designer's Interface'' (0.3 MByte pdf file) , IEEE Circuits & Devices Magazine, vol. 20, nr. 4, pp. 3-4, July, 2004.
Bouldin, D., W. Snapp, P. Haug, D. Sunderland, R. Brees, C. Sechen and W. Dai, ``ASIC By Design'' (1.2 MByte pdf file) , IEEE Circuits & Devices Magazine, vol. 20, nr. 4, pp. 17-21, July, 2004.
Srivastava, R., ``Development of An Open Core System-on-Chip Platform'' (4.3 MByte pdf file) , M.S. Thesis, University of Tennessee, August 2004.
Balakrishnan, A., ``An Experimental Study of the Accuracy of Multiple Power Estimation Methods'' (2.3 MByte pdf file) , M.S. Thesis, University of Tennessee, August 2004.
Devalapalli, S., ``Development of SystemC Modules from HDL for System-on-Chip Applications'' (1 MByte pdf file) , M.S. Thesis, University of Tennessee, May 2004.
Patel, K., ``Quality and Versatility of Automatic Leafcell Generation'' (1.3 MByte pdf file) , M.S. 501 Project, University of Tennessee, May 2004.
Raghuraman, N., ``Animating Logic Simulations'' (0.8 MByte pdf file) , M.S. 501 Project, University of Tennessee, May 2004.
Earl, D., ``Development of an FPGA-based Hardware Evaluation System for use with GA-designed Artificial Neural Networks'' (2.2 MByte pdf file) , Ph.D. Dissertation, University of Tennessee, May 2004.
Karakaya, F., ``Automated Exploration of the ASIC Design Space for Minimum Power-Delay-Area Product at the Register Transfer Level'' (3.6 MByte pdf file) , Ph.D. Dissertation, University of Tennessee, May 2004.
Bouldin, D., ``Impacting Education Using FPGAs'' (0.3 MByte pdf file) , Proceedings of 2004 Reconfigurable Architectures Workshop (RAW), Santa Fe, NM, April 26-27, 2004.
Bouldin, D., Tan, C. and K. Patel, ``Teaching Custom and Automated Cell Design'' (0.3 MByte pdf file) , Proceedings of 2004 European Workshop on Microelectronics Education (EWME), Lausanne, Switzerland, April 15-16, 2004.
Bouldin, D. and R. Srivastava, ``An Open System-on-Chip Platform for Education'' (0.5 MByte pdf file) , Proceedings of 2004 European Workshop on Microelectronics Education (EWME), Lausanne, Switzerland, April 15-16, 2004.
Miller, A., ``Development and Verification of Parameterized Digital Signal Processing Macros for Microelectronic Systems'' (1 MByte pdf file) , M.S. Thesis, University of Tennessee, August 2003.
Fu, X., ``Development and Verification of the Data Encryption Standard for ASICs and FPGAs'' (0.8 MByte pdf file) , M.S. Thesis, University of Tennessee, August 2003.
Bouldin, D., Miller, A. and C. Tan, ``Teaching Custom IC Design and Verification'' (66 KByte pdf file) , Proceedings of 2003 Microelectronic Systems Education Conference (MSE), Anaheim, CA, pp. 48-49, June 1-2, 2003.
Bouldin, D., ``Platform-Based System-on-Chip Design'' (506 KByte pdf file) , Proceedings of 2003 NASA Symposium on VLSI Design , Cour d'Alene, ID, pp. 1-4, May 28-29, 2003.
Snapp, W., Haug, P., Sunderland, D., Brees, R., Bouldin, D., Sechen, C. and W. Dai, ``MSP Liberator ASIC Design Flow Produces Full Custom Performance Required for Next Generation Military Electronics'' (377 KByte pdf file) , Proceedings of 2003 Government Microcircuit Applications Conference (GOMAC), pp. 498-501, Tampa, FL, April 3, 2003.
Bouldin, D. and G. Peterson, ``Implementing Applications Using Reconfigurable Electronic Systems'' (303 KByte pdf file) , Proceedings of 2003 Government Microcircuit Applications Conference (GOMAC), pp. 544-547, Tampa, FL, April 3, 2003.
Peterson, G. and S. Drager, ``Accelerating Defense Applications Using High Performance Reconfigurable Computing'' (196 KByte pdf file) , Proceedings of 2003 Government Microcircuit Applications Conference (GOMAC), pp. 398-401, Tampa, FL, April 3, 2003.
Ku, Chung ``Size, Speed and Power Analysis for Application-specific Integrated Circuits Using Synthesis '' (1.9 MByte pdf file) , M.S. Thesis, University of Tennessee, May 2003.
McCollum, M., Lancaster, J., Bouldin, D. and G. Peterson, ``Hardware Acceleration of Pseudo-Random Number Generation for Simulation Applications,'' (40 KByte pdf) , Proceedings of the 35th Annual Southeastern Symposium on System Theory, Morgantown, WV, pp. 299-303, March 16-18, 2003.
Koay, T., ``Verification of Intellectual Property Blocks Using Reconfigurable Hardware '' (1.3 MByte pdf file) ,M.S. Thesis, University of Tennessee, December 2002.
Newport, D. and D. Bouldin, ``Using Configurable Computing Systems '' (0.1 MByte pdf) , Computer Engineering Handbook, Edited by Vojin Oklobdzija, CRC Press, pp. 37-17 thru 37-24 (2001).
Ong, S., Kerkiz, N., Srijanto, B., Tan, C., Langston, M., Newport, D. and D. Bouldin, ``Automatic Mapping of Multiple Applications to Multiple Adaptive Computing Systems '' (166 KByte pdf) , Proceedings of 2001 IEEE Symposium on Field-programmable Custom Computing Machines (FCCM), pp. 218-227, Rohnert, CA, April 30, 2001.
Ong, S., Kerkiz, N., Srijanto, B., Tan, C., Langston, M., Newport, D. and D. Bouldin, ``Design Flow for Automatic Mapping of Graphical Programming Applications to Adaptive Computing Systems '' (37 KByte pdf file) , Proceedings of the High Performance Embedded Computing Workshop (HPEC), Boston, MA, Sep. 23, 2000.
Bouldin, D., ``Enhancing System-level Education with Reusable Designs '' (13 KByte pdf file) , Proceedings of European Workshop on Microelectronics Education (EWME), Kluwer Academic Publishers, pp. 5-8, Aix-en-Provence, FRANCE, May 18, 2000.
Kelly, M. and D. Bouldin, ``Verification of Portable Intellectual Property Blocks for FPGAs '' (360 KByte pdf file) , Proceedings of 2000 IEEE Southeastern Conference (SECON), pp. 531-534, Nashville, TN, April 9, 2000.
Bouldin, D., ``Collaborative Efforts to Support System-Level Design Education '' (104 KByte pdf file) , Proceedings of 1999 Collaborative Technologies Workshop (COLLAB), pp. 200-203, Rochester, MI, Nov. 10-11, 1999.
Natarajan, S., Levine, B., Tan, C., Newport, D. and D. Bouldin, ``Automatic Mapping of Khoros-based Applications to Adaptive Computing Systems'' (72 KByte pdf file) , Proceedings of 1999 Military and Aerospace Applications of Programmable Devices and Technologies International Conference (MAPLD) , pp. 101-107, Laurel, MD, Sept. 28-30, 1999.
Levine, B., ``A System for the Implementation of Image Processing Algorithms on Configurable Computing Hardware'' (43 KByte pdf file) , M.S. Thesis, University of Tennessee, August 1999.
Natarajan, S., `` Development and Verification of Library Cells for Reconfigurable Logic '' (622 KByte pdf file) , M.S. Thesis, University of Tennessee, August 1999.
Shetters, C., `` Scheduling Task Chains on an Array of Reconfigurable FPGAs '' (371 KByte pdf file) , M.S. Thesis, University of Tennessee Space Institute, December 1999.
Bouldin, D., Natarajan, S., Levine, B., Tan, C. and D. Newport, ``Training IP Creators and Integrators'' (48 KByte pdf file) , Proceedings of 1999 Microelectronic Systems Education Conference (MSE), pp. 4-5, Arlington, VA, July 19-21, 1999.
Levine, B., Natarajan, S., Tan, C., Newport, D. and D. Bouldin, ``Mapping of an Automated Target Recognition Application from a Graphical Software Environment to FPGA-based Reconfigurable Hardware'' (31 KByte pdf file) , Proceedings of 1999 IEEE Symposium on Field-programmable Custom Computing Machines (FCCM), pp. 292-293, Napa, CA, April 21-23, 1999.
Simpson, M., Rochelle, J., Bouldin, D., Paulus, M., Blalock, V., Bryan, W., Kennedy, E., Britton, C., Roberts, M., Wintenberg, A., Karim, M., Alley, G., Ericson, N. and M. Bobrek, ``Collaborative Graduate Education: The University of Tennessee/Oak Ridge National Laboratory Joint Program Mixed-Signal VLSI and Monolithic Sensors'' (179 KByte pdf file), , Proceedings of 1999 Southwest Symposium on Mixed-Signal Design (SSMSD) , pp. 74-76, Tuscon, AZ, April 11-13, 1999.
Bouldin, D., ``Microelectronic Systems Education in the United States'' (103 KByte pdf file) , Proceedings of 1998 European Workshop on Microelectronics Education (EWME) , pp. 64-70, Noordwijkerhout, The Netherlands, May 14-15, 1998.
York, J., Powell, T., Dehkordi, P. and D. Bouldin, ``Enhancement of MCM Testability Using an Embedded Reconfigurable FPGA'' , Proceedings of 1997 International Conference on Innovative Systems in Silicon, pp. 165-173, Austin, TX, October 8-10, 1997.