-- IEEE Library
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
ENTITY DCT_Fofx IS
--generic value for the number of bits ofr the input and the output
generic (n:integer :=16); --no of bits
PORT(

	Clk			: IN	STD_LOGIC;		-- Global Clk
	Reset		: IN	STD_LOGIC;		-- Global Reset
	--in from the controller 
	Cont_Reg_En 	:IN STD_LOGIC_VECTOR (7 downto 0);
	Cont_MUX_Enable :IN STD_LOGIC_VECTOR (2 downto 0);
	--in to the Reg 
	fx1		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx2		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx3		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx4		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx5		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx6		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx7		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx8		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	-- out of the mux
	Mux_OUT		: OUT STD_LOGIC_VECTOR (n-1 downto 0)
	);
END DCT_Fofx;

architecture DCT_Fofx_arch of DCT_Fofx is
	-- signals i.e the output of the Reg
	signal fx1_out_sig :STD_LOGIC_VECTOR (n-1 downto 0):= (others => '0');
	signal fx2_out_sig :STD_LOGIC_VECTOR (n-1 downto 0):=(others => '0');
	signal fx3_out_sig :STD_LOGIC_VECTOR (n-1 downto 0):=(others => '0');
	signal fx4_out_sig :STD_LOGIC_VECTOR (n-1 downto 0):=(others => '0');
	signal fx5_out_sig :STD_LOGIC_VECTOR (n-1 downto 0):=(others => '0');
	signal fx6_out_sig :STD_LOGIC_VECTOR (n-1 downto 0):=(others => '0');
	signal fx7_out_sig :STD_LOGIC_VECTOR (n-1 downto 0):=(others => '0');
	signal fx8_out_sig :STD_LOGIC_VECTOR (n-1 downto 0):=(others => '0');
	
	

--Component declaration of DCT_Reg
COMPONENT DCT_Reg
PORT(
		Reg_In		: IN	STD_LOGIC_VECTOR(n-1 downto 0);
		Clk			: IN	STD_LOGIC;
		Reset		: IN	STD_LOGIC;
		Reg_En		: IN	STD_LOGIC;
		Reg_Out		: OUT 	STD_LOGIC_VECTOR(n-1 downto 0) 
	);
END COMPONENT;

begin
--Portmap
DCT_REG_1:DCT_Reg 
	PORT MAP (
		Reg_In => fx1,
		Reg_Out => fx1_out_sig,
		Reset => Reset,
		Reg_En => Cont_Reg_En(0),
		Clk => Clk
		);
DCT_REG_2:DCT_Reg 
	PORT MAP (
		Reg_In => fx2,
		Reg_Out => fx2_out_sig,
		Reset => Reset,
		Reg_En => Cont_Reg_En(1),
		Clk => Clk
		);
DCT_REG_3:DCT_Reg 
	PORT MAP (
		Reg_In => fx3,
		Reg_Out => fx3_out_sig,
		Reset => Reset,
		Reg_En => Cont_Reg_En(2),
		Clk => Clk
		);
DCT_REG_4:DCT_Reg 
	PORT MAP (
		Reg_In => fx4,
		Reg_Out => fx4_out_sig,
		Reset => Reset,
		Reg_En => Cont_Reg_En(3),
		Clk => Clk
		);
		
DCT_REG_5:DCT_Reg 
	PORT MAP (
		Reg_In => fx5,
		Reg_Out => fx5_out_sig,
		Reset => Reset,
		Reg_En => Cont_Reg_En(4),
		Clk => Clk
		);
DCT_REG_6:DCT_Reg 
	PORT MAP (
		Reg_In => fx6,
		Reg_Out => fx6_out_sig,
		Reset => Reset,
		Reg_En => Cont_Reg_En(5),
		Clk => Clk
		);
DCT_REG_7:DCT_Reg 
	PORT MAP (
		Reg_In => fx7,
		Reg_Out => fx7_out_sig,
		Reset => Reset,
		Reg_En => Cont_Reg_En(6),
		Clk => Clk
		);
DCT_REG_8:DCT_Reg 
	PORT MAP (
		Reg_In => fx8,
		Reg_Out => fx8_out_sig,
		Reset => Reset,
		Reg_En => Cont_Reg_En(7),
		Clk => Clk
		);


process(Cont_MUX_Enable,fx1_out_sig,fx2_out_sig,fx3_out_sig,fx4_out_sig,fx5_out_sig,fx6_out_sig,fx7_out_sig,fx8_out_sig)
begin
--MUX which gives the needed output according to the Cont_MUX_Enable
case Cont_MUX_Enable is

	when "000" =>
		Mux_OUT <= fx1_out_sig;
		
	
	when "001" =>
		Mux_OUT <= fx2_out_sig;
		
		
	when "010" =>
		Mux_OUT <= fx3_out_sig;
				
	when "011" =>
		Mux_OUT <= fx4_out_sig;
				
	when "100" =>
		Mux_OUT <= fx5_out_sig;
				
	when "101" =>
		Mux_OUT <= fx6_out_sig;
				
	when "110" =>
		Mux_OUT <= fx7_out_sig;
				
	when "111" =>
		Mux_OUT <= fx8_out_sig;
		
	when others => 
		Mux_OUT <= (others => '0'); 

end case;

end process;

end DCT_Fofx_arch;