-- IEEE Library
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

ENTITY DCT_Parallel_Controller IS
--Generic parameters
generic (n: integer := 16;		-- Number of bits of input data
	 m: integer := 36);		-- Number of bits of INput data
PORT(

	-- Global System Inputs
	Clk: IN	STD_LOGIC;		-- Global Clk
	Reset: IN	STD_LOGIC;	-- Global Reset
		
	--Inputs from the Main module
	Start: IN STD_LOGIC;

	--Output to the Main Module
	Done: OUT STD_LOGIC;
	
	-- Outputs to DCT_Cos
	Cos_Mux_Sel: OUT STD_LOGIC_VECTOR (2 downto 0);

	--Outputs to DCT_Cos and DCT_fofx
	Mux1_En: OUT STD_LOGIC_VECTOR (2 downto 0);
	Reg1_En: OUT STD_LOGIC_VECTOR (7 downto 0);

	--Outputs to Register that store f(x) and Cos(x)
	Reg2_En: OUT STD_LOGIC;

	--Inputs from DCT_Calc
	Negative1: IN STD_LOGIC;
	Negative2: IN STD_LOGIC;
	Negative3: IN STD_LOGIC;
	Negative4: IN STD_LOGIC;
	Negative5: IN STD_LOGIC;
	Negative6: IN STD_LOGIC;
	Negative7: IN STD_LOGIC;
	Negative8: IN STD_LOGIC;

	--Outputs to DCT_Calc
	Neg_Reg_En1: OUT STD_LOGIC; 
	Neg_Reg_En2: OUT STD_LOGIC;
	Neg_Reg_En3: OUT STD_LOGIC;
	Neg_Reg_En4: OUT STD_LOGIC;
	Neg_Reg_En5: OUT STD_LOGIC; 
	Neg_Reg_En6: OUT STD_LOGIC;
	Neg_Reg_En7: OUT STD_LOGIC;
	Neg_Reg_En8: OUT STD_LOGIC;

	Mult_Reg_En: OUT STD_LOGIC;	--Enable signal for Mult_Reg

	Mult_Sel1: OUT STD_LOGIC;
	Mult_Sel2: OUT STD_LOGIC;
	Mult_Sel3: OUT STD_LOGIC;
	Mult_Sel4: OUT STD_LOGIC;
	Mult_Sel5: OUT STD_LOGIC;
	Mult_Sel6: OUT STD_LOGIC;
	Mult_Sel7: OUT STD_LOGIC;
	Mult_Sel8: OUT STD_LOGIC;	
	
	SOP_Reg_En: OUT STD_LOGIC;	--Enable signal for SOP_Reg

	Output_Sel1: OUT STD_LOGIC;
	Output_Sel2: OUT STD_LOGIC;
	Output_Sel3: OUT STD_LOGIC;
	Output_Sel4: OUT STD_LOGIC;
	Output_Sel5: OUT STD_LOGIC;
	Output_Sel6: OUT STD_LOGIC;
	Output_Sel7: OUT STD_LOGIC;
	Output_Sel8: OUT STD_LOGIC;
	
	Clr_SOP_Reg: OUT STD_LOGIC
	);
END DCT_Parallel_Controller;

architecture DCT_Parallel_Controller_arch of DCT_Parallel_Controller is

--Signals related to Count_Eight_2
signal Count_Eight_2, Cnt_Eight_2: STD_LOGIC_VECTOR(2 downto 0);
signal Clr_Cnt_Eight_2, Inc_Cnt_Eight_2:STD_LOGIC;

--Signals related to Detect_x0
signal Zero: STD_LOGIC;

-- Controller FSM states
type STATE_TYPE is (Idle, Register_Select, Mux_Select, Store_Inputs, Store_Neg, Store_Mult, Select_Mult, Store_SOP, Select_Output);
signal CurrentState, NextState: STATE_TYPE;

begin

-- Debug 

-- Controller FSM
State_machine: process(CurrentState, Start, Cnt_Eight_2, Negative1, Negative2, Negative3, Negative4, Negative5, Negative6, Negative7, Negative8)
begin

-- Default all outputs to FALSE
Inc_Cnt_Eight_2 <= '0'; Clr_Cnt_Eight_2 <= '0';
Done <= '0';
Cos_Mux_Sel <= "000";
Mux1_En <= "000"; Reg1_En <= "00000000";
Reg2_En <= '0';
Neg_Reg_En1 <= '0'; Neg_Reg_En2 <= '0';	Neg_Reg_En3 <= '0'; Neg_Reg_En4 <= '0'; Neg_Reg_En5 <= '0'; Neg_Reg_En6 <= '0'; Neg_Reg_En7 <= '0'; Neg_Reg_En8 <= '0'; 
Mult_Reg_En <= '0'; 
Mult_Sel1 <= '0'; Mult_Sel2 <= '0'; Mult_Sel3 <= '0'; Mult_Sel4 <= '0'; Mult_Sel5 <= '0'; Mult_Sel6 <= '0'; Mult_Sel7 <= '0'; Mult_Sel8 <= '0';
SOP_Reg_En <= '0'; Clr_SOP_Reg <= '0';

case CurrentState is

	when Idle =>
		if (Start = '1') then
			NextState <= Register_Select;
		else
			NextState <= Idle;
		end if;
	
--	when Cos_Select =>
--		Cos_Mux2_En <= Cnt_Eight_1;
--		NextState <= Register_Select;
	
	when Register_Select =>
--		Inc_Cnt_Eight_1 <= '1';
		Reg1_En <= "11111111";
		NextState <= Mux_Select;

	when Mux_Select =>
		Mux1_En <= Cnt_Eight_2;
		Cos_Mux_Sel <= Cnt_Eight_2;
		NextState <= Store_Inputs;

	when Store_Inputs =>
--		Inc_Cnt_Eight_2 <= '1';
		Mux1_En <= Cnt_Eight_2;
		Cos_Mux_Sel <= Cnt_Eight_2;
		Reg2_En <= '1';
		NextState <= Store_Neg;

	when Store_Neg =>
		Neg_Reg_En1 <= '1';
		Neg_Reg_En2 <= '1';
		Neg_Reg_En3 <= '1';
		Neg_Reg_En4 <= '1';
		Neg_Reg_En5 <= '1'; 
		Neg_Reg_En6 <= '1';
		Neg_Reg_En7 <= '1';
		Neg_Reg_En8 <= '1';
		NextState <= Store_Mult;

	when Store_Mult =>
		Mult_Reg_En <= '1';
		NextState <= Select_Mult;

	when Select_Mult =>
		if (Negative1 = '1') then
			Mult_Sel1 <= '1';
		else
			Mult_Sel1 <= '0';
		end if;
		if (Negative2 = '1') then
			Mult_Sel2 <= '1';
		else
			Mult_Sel2 <= '0';
		end if;
		if (Negative3 = '1') then
			Mult_Sel3 <= '1';
		else
			Mult_Sel3 <= '0';
		end if;
		if (Negative4 = '1') then
			Mult_Sel4 <= '1';
		else
			Mult_Sel4 <= '0';
		end if;
		if (Negative5 = '1') then
			Mult_Sel5 <= '1';
		else
			Mult_Sel5 <= '0';
		end if;
		if (Negative6 = '1') then
			Mult_Sel6 <= '1';
		else
			Mult_Sel6 <= '0';
		end if;
		if (Negative7 = '1') then
			Mult_Sel7 <= '1';
		else
			Mult_Sel7 <= '0';
		end if;
		if (Negative8 = '1') then
			Mult_Sel8 <= '1';
		else
			Mult_Sel8 <= '0';
		end if;
		NextState <= Store_SOP;

	when Store_SOP =>
		if (Negative1 = '1') then
			Mult_Sel1 <= '1';
		else
			Mult_Sel1 <= '0';
		end if;
		if (Negative2 = '1') then
			Mult_Sel2 <= '1';
		else
			Mult_Sel2 <= '0';
		end if;
		if (Negative3 = '1') then
			Mult_Sel3 <= '1';
		else
			Mult_Sel3 <= '0';
		end if;
		if (Negative4 = '1') then
			Mult_Sel4 <= '1';
		else
			Mult_Sel4 <= '0';
		end if;
		if (Negative5 = '1') then
			Mult_Sel5 <= '1';
		else
			Mult_Sel5 <= '0';
		end if;
		if (Negative6 = '1') then
			Mult_Sel6 <= '1';
		else
			Mult_Sel6 <= '0';
		end if;
		if (Negative7 = '1') then
			Mult_Sel7 <= '1';
		else
			Mult_Sel7 <= '0';
		end if;
		if (Negative8 = '1') then
			Mult_Sel8 <= '1';
		else
			Mult_Sel8 <= '0';
		end if;		
		SOP_Reg_En <= '1';
		NextState <= Select_Output;

	when Select_Output =>
				
		if (Cnt_Eight_2 = "111") then
			Clr_Cnt_Eight_2 <= '1';
--			Inc_Cnt_Eight_1 <= '1';
			Clr_SOP_Reg <= '1';
			Done <= '1';
			NextState <= Idle;
		else
			Clr_SOP_Reg <= '0';
			Inc_Cnt_Eight_2 <= '1';
			NextState <= Mux_Select;
		end if;		
	when others =>
		NextState <= Idle;

end case;

end process;

-- To synchorinize the statemachine with Global Clk
State_Sync:process (Clk, Reset)
begin
    if (Reset='1') then
        CurrentState <= Idle;
    elsif (Clk'event and Clk = '1') then
        CurrentState <= NextState;
	end if;
end process;

Counter_Eight_2:process (Clk, Reset, Cnt_Eight_2, Clr_Cnt_Eight_2)
begin
    if (Reset='1') then
        Count_Eight_2 <= "000";
    elsif (Clk'event and Clk = '1') then
		if (Clr_Cnt_Eight_2 = '1') then
			Count_Eight_2 <= "000";
		elsif (Inc_Cnt_Eight_2 = '1') then
			Count_Eight_2 <= Count_Eight_2 + "001";
		end if;
    end if;
end process;
Cnt_Eight_2 <= Count_Eight_2;

	Output_Sel1 <= '1';
	Output_Sel2 <= '0';
	Output_Sel3 <= '0';
	Output_Sel4 <= '0';
	Output_Sel5 <= '0';
	Output_Sel6 <= '0';
	Output_Sel7 <= '0';
	Output_Sel8 <= '0';

end DCT_Parallel_Controller_arch;