-- IEEE Library
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

ENTITY DCT_Parallel_Main1 IS
--generic value for the number of bits ofr the input and the output
generic (n: integer := 16;
	 m: integer:= 36);
PORT(

	Clk: IN	STD_LOGIC;		-- Global Clk
	Reset: IN STD_LOGIC;		-- Global Reset
	--from the controller
	Reg_En: IN STD_LOGIC;		--enable for the reg to DCT_Calc
	--output from DCT_Fofx as an input 	
	--for the DCT_Fofx 
	Cont_Reg_En:IN STD_LOGIC_VECTOR (7 downto 0);
	Cont_MUX_Enable:IN STD_LOGIC_VECTOR (2 downto 0);
	fx1:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx2:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx3:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx4:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx5:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx6:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx7:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx8:IN STD_LOGIC_VECTOR (n-1 downto 0);
	--for DCT_parallel 
	Cos_Mux_Sel	:IN STD_LOGIC_VECTOR (2 downto 0); --from controller
	--in for the DCT_Calc
	--from the controller
	Mult_Reg_En: IN STD_LOGIC; --Signals related to Mult_Reg
	Neg_Reg_En_1: IN STD_LOGIC; 
	Neg_Reg_En_2: IN STD_LOGIC;
	Neg_Reg_En_3: IN STD_LOGIC;
	Neg_Reg_En_4: IN STD_LOGIC;
	Neg_Reg_En_5: IN STD_LOGIC; 
	Neg_Reg_En_6: IN STD_LOGIC;
	Neg_Reg_En_7: IN STD_LOGIC;
	Neg_Reg_En_8: IN STD_LOGIC;
	Mult_Sel_1: IN STD_LOGIC;
	Mult_Sel_2: IN STD_LOGIC;
	Mult_Sel_3: IN STD_LOGIC;
	Mult_Sel_4: IN STD_LOGIC;
	Mult_Sel_5: IN STD_LOGIC;
	Mult_Sel_6: IN STD_LOGIC;
	Mult_Sel_7: IN STD_LOGIC;
	Mult_Sel_8: IN STD_LOGIC;
	SOP_Reg_En: IN STD_LOGIC;
	--output select
	Output_Sel_1: IN STD_LOGIC;
	Output_Sel_2: IN STD_LOGIC;
	Output_Sel_3: IN STD_LOGIC;
	Output_Sel_4: IN STD_LOGIC;
	Output_Sel_5: IN STD_LOGIC;
	Output_Sel_6: IN STD_LOGIC;
	Output_Sel_7: IN STD_LOGIC;
	Output_Sel_8: IN STD_LOGIC;
	--out of the DCT_main
	Negative_1: OUT STD_LOGIC;
	Negative_2: OUT STD_LOGIC;
	Negative_3: OUT STD_LOGIC;
	Negative_4: OUT STD_LOGIC;
	Negative_5: OUT STD_LOGIC;
	Negative_6: OUT STD_LOGIC;
	Negative_7: OUT STD_LOGIC;
	Negative_8: OUT STD_LOGIC;
	FofX_1:Out STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_2:OUT STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_3:Out STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_4:OUT STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_5:Out STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_6:OUT STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_7:Out STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_8:Out STD_LOGIC_VECTOR (m-1 downto 0);
	Clr_SOP_Reg: IN STD_LOGIC
	);
END DCT_Parallel_Main1;

architecture DCT_Parallel_Main1_arch of DCT_Parallel_Main1 is

signal  mux_sig_out	: STD_LOGIC_VECTOR (n-1 downto 0);

signal  cos1		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos2		: STD_LOGIC_VECTOR (n-1 downto 0); 
signal  cos3		: STD_LOGIC_VECTOR (n-1 downto 0); 
signal  cos4		: STD_LOGIC_VECTOR (n-1 downto 0); 
signal  cos5		: STD_LOGIC_VECTOR (n-1 downto 0); 
signal  cos6		: STD_LOGIC_VECTOR (n-1 downto 0); 
signal  cos7		: STD_LOGIC_VECTOR (n-1 downto 0); 
signal  cos8		: STD_LOGIC_VECTOR (n-1 downto 0); 

signal  cos9		: STD_LOGIC_VECTOR (n-1 downto 0); 
signal  cos10		: STD_LOGIC_VECTOR (n-1 downto 0); 
signal  cos11		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos12		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos13		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos14		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos15		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos16		: STD_LOGIC_VECTOR (n-1 downto 0);

signal  cos17		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos18		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos19		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos20		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos21		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos22		: STD_LOGIC_VECTOR (n-1 downto 0); 
signal  cos23		: STD_LOGIC_VECTOR (n-1 downto 0); 
signal  cos24		: STD_LOGIC_VECTOR (n-1 downto 0); 

signal  cos25		: STD_LOGIC_VECTOR (n-1 downto 0); 
signal  cos26		: STD_LOGIC_VECTOR (n-1 downto 0); 
signal  cos27		: STD_LOGIC_VECTOR (n-1 downto 0); 
signal  cos28		: STD_LOGIC_VECTOR (n-1 downto 0); 
signal  cos29		: STD_LOGIC_VECTOR (n-1 downto 0); 
signal  cos30		: STD_LOGIC_VECTOR (n-1 downto 0); 
signal  cos31		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos32		: STD_LOGIC_VECTOR (n-1 downto 0);

signal  cos33		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos34		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos35		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos36		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos37		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos38		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos39		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos40		: STD_LOGIC_VECTOR (n-1 downto 0);

signal  cos41		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos42		: STD_LOGIC_VECTOR (n-1 downto 0); 
signal  cos43		: STD_LOGIC_VECTOR (n-1 downto 0); 
signal  cos44		: STD_LOGIC_VECTOR (n-1 downto 0); 
signal  cos45		: STD_LOGIC_VECTOR (n-1 downto 0); 
signal  cos46		: STD_LOGIC_VECTOR (n-1 downto 0); 
signal  cos47		: STD_LOGIC_VECTOR (n-1 downto 0); 
signal  cos48		: STD_LOGIC_VECTOR (n-1 downto 0); 

signal  cos49		: STD_LOGIC_VECTOR (n-1 downto 0); 
signal  cos50		: STD_LOGIC_VECTOR (n-1 downto 0); 
signal  cos51		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos52		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos53		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos54		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos55		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos56		: STD_LOGIC_VECTOR (n-1 downto 0);

signal  cos57		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos58		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos59		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos60		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos61		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos62		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos63		: STD_LOGIC_VECTOR (n-1 downto 0);
signal  cos64		: STD_LOGIC_VECTOR (n-1 downto 0);

--Component declaration of DCT_Fofx
COMPONENT DCT_Fofx
PORT(
	Clk		: IN	STD_LOGIC;		-- Global Clk
	Reset		: IN	STD_LOGIC;		-- Global Reset
	--in from the controller 
	Cont_Reg_En 	:IN STD_LOGIC_VECTOR (7 downto 0);
	Cont_MUX_Enable :IN STD_LOGIC_VECTOR (2 downto 0);
	--in to the Reg 
	fx1		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx2		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx3		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx4		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx5		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx6		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx7		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx8		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	-- out of the mux
	Mux_OUT		: OUT STD_LOGIC_VECTOR (n-1 downto 0)
);
END COMPONENT;

--component declaration of DCT_parallel
COMPONENT DCT_parallel
PORT(
	Clk				: IN	STD_LOGIC;		-- Global Clk
	Reset				: IN	STD_LOGIC;		-- Global Reset
	--from the controller
	Reg_En				: IN	STD_LOGIC;		--enable for the reg to DCT_Calc
	--output from DCT_Fofx as an input 	
	Mux_OUT				: IN STD_LOGIC_VECTOR (n-1 downto 0);
	--input for the cos_mux
	cos_1				:IN STD_LOGIC_VECTOR (n-1 downto 0);
	cos_2				:IN STD_LOGIC_VECTOR (n-1 downto 0);
	cos_3				:IN STD_LOGIC_VECTOR (n-1 downto 0);
	cos_4				:IN STD_LOGIC_VECTOR (n-1 downto 0);
	cos_5				:IN STD_LOGIC_VECTOR (n-1 downto 0);
	cos_6				:IN STD_LOGIC_VECTOR (n-1 downto 0);
	cos_7				:IN STD_LOGIC_VECTOR (n-1 downto 0);
	cos_8				:IN STD_LOGIC_VECTOR (n-1 downto 0);
	--MUX to select the values for cos_mux 
	Cos_Mux_Sel	:IN STD_LOGIC_VECTOR (2 downto 0); --from controller
	--in for the DCT_Calc
	--from the controller
	Mult_Reg_En: IN STD_LOGIC; --Signals related to Mult_Reg
	Neg_Reg_En: IN STD_LOGIC; --Signals related to Neg_Reg
	Mult_Sel: IN STD_LOGIC;
	SOP_Reg_En: IN STD_LOGIC;
	Output_Sel: IN STD_LOGIC;
	Clr_SOP_Reg: IN STD_LOGIC;
	--out of the DCT_main
	FofX_Out 			: OUT STD_LOGIC_VECTOR (m-1 downto 0); -- F(u) output
	Negative_Out			: OUT STD_LOGIC
		);
END COMPONENT;

begin

cos1  <= "0000000010000000";
cos2  <= "0000000010000000"; 
cos3  <= "0000000010000000"; 
cos4  <= "0000000010000000"; 
cos5  <= "0000000010000000"; 
cos6  <= "0000000010000000"; 
cos7  <= "0000000010001000"; 
cos8  <= "0000000010000000"; 

cos9  <= "0000000001111101"; 
cos10  <= "0000000001101010"; 
cos11  <= "0000000001000111";
cos12  <= "0000000000011000";
cos13  <= "1000000000011000";
cos14  <= "1000000001000111";
cos15  <= "1000000001101010";
cos16  <= "1000000001111101";

cos17  <= "0000000001110110";
cos18  <= "0000000000110000";
cos19  <= "1000000000110000";
cos20  <= "1000000001110110";
cos21  <= "1000000001110110";
cos22  <= "1000000000110000"; 
cos23  <= "0000000000110000"; 
cos24  <= "0000000001110110"; 

cos25  <= "0000000001101010"; 
cos26  <= "1000000000011000"; 
cos27  <= "1000000001111101"; 
cos28  <= "1000000001000111"; 
cos29  <= "0000000001000111"; 
cos30  <= "0000000001111101"; 
cos31  <= "0000000000011000";
cos32  <= "1000000001101010";

cos33  <= "0000000001011010";
cos34  <= "1000000001011010";
cos35  <= "1000000001011010";
cos36  <= "0000000001011010";
cos37  <= "0000000001011010";
cos38  <= "1000000001011010";
cos39  <= "1000000001011010";
cos40  <= "0000000001011010";

cos41  <= "0000000001000111";
cos42  <= "1000000001111101"; 
cos43  <= "0000000000011000"; 
cos44  <= "0000000001101010"; 
cos45  <= "1000000001101010"; 
cos46  <= "1000000000011000"; 
cos47  <= "0000000001111101"; 
cos48  <= "1000000001000111"; 

cos49  <= "0000000000110000"; 
cos50  <= "1000000001110110"; 
cos51  <= "0000000001110110";
cos52  <= "1000000000110000";
cos53  <= "1000000000110000";
cos54  <= "0000000001110110";
cos55  <= "1000000001110110";
cos56  <= "0000000000110000";

cos57  <= "0000000000011000";
cos58  <= "1000000001000111";
cos59  <= "0000000001101010";
cos60  <= "1000000001111101";
cos61  <= "0000000001111101";
cos62  <= "1000000001101010";
cos63  <= "0000000001000111";
cos64  <= "1000000000011000";



--Portmap DCT_Fofx
DCT_Fofx_1: DCT_Fofx 
	PORT MAP (
	Clk => Clk,			
	Reset => Reset,	
	--in from the controller 
	Cont_Reg_En => Cont_Reg_En,
	Cont_MUX_Enable => Cont_MUX_Enable,
	--in to the Reg 
	fx1		=> fx1,
	fx2		=> fx2,
	fx3		=> fx3,
	fx4		=> fx4,
	fx5		=> fx5,
	fx6		=> fx6,
	fx7		=> fx7,
	fx8		=> fx8,
	-- out of the mux
	Mux_OUT	=> mux_sig_out
		);

DCT_parallel_1: DCT_parallel
PORT MAP (
	Clk => Clk,			
	Reset => Reset,
	Reg_En	=> Reg_En,			
	Mux_OUT	=> mux_sig_out,			
	--input for the cos_mux1
	 cos_1 => cos1,
	 cos_2 => cos2,
	 cos_3 => cos3,
	 cos_4 => cos4,
	 cos_5 => cos5,
	 cos_6 => cos6,
	 cos_7 => cos7,
	 cos_8 => cos8,
	Cos_Mux_Sel	=> Cos_Mux_Sel,
	Mult_Reg_En => Mult_Reg_En,
	Neg_Reg_En	=> Neg_Reg_En_1,
	Mult_Sel 	=> Mult_Sel_1,
	SOP_Reg_En	=> SOP_Reg_En,
	Output_Sel => Output_Sel_1,
	FofX_Out 	=> FofX_1,
	Clr_SOP_Reg => Clr_SOP_Reg,	
	Negative_Out => Negative_1
		);

DCT_parallel_2: DCT_parallel
PORT MAP (
	Clk => Clk,			
	Reset => Reset,
	Reg_En	=> Reg_En,			
	Mux_OUT	=> mux_sig_out,			
	--input for the cos_mux1
	 cos_1 => cos9,
	 cos_2 => cos10,
	 cos_3 => cos11,
	 cos_4 => cos12,
	 cos_5 => cos13,
	 cos_6 => cos14,
	 cos_7 => cos15,
	 cos_8 => cos16,
	Cos_Mux_Sel	=> Cos_Mux_Sel,
	Mult_Reg_En => Mult_Reg_En,
	Neg_Reg_En	=> Neg_Reg_En_2,
	Mult_Sel 	=> Mult_Sel_2,
	SOP_Reg_En	=> SOP_Reg_En,
	Output_Sel => Output_Sel_2,
	FofX_Out 	=> FofX_2,
	Clr_SOP_Reg => Clr_SOP_Reg,		
	Negative_Out => Negative_2
		);

DCT_parallel_3: DCT_parallel
PORT MAP (
	Clk => Clk,			
	Reset => Reset,
	Reg_En	=> Reg_En,			
	Mux_OUT	=> mux_sig_out,			
	--input for the cos_mux1
	 cos_1 => cos17,
	 cos_2 => cos18,
	 cos_3 => cos19,
	 cos_4 => cos20,
	 cos_5 => cos21,
	 cos_6 => cos22,
	 cos_7 => cos23,
	 cos_8 => cos24,
	Cos_Mux_Sel	=> Cos_Mux_Sel,
	Mult_Reg_En => Mult_Reg_En,
	Neg_Reg_En	=> Neg_Reg_En_3,
	Mult_Sel 	=> Mult_Sel_3,
	SOP_Reg_En	=> SOP_Reg_En,
	Output_Sel => Output_Sel_3,
	FofX_Out 	=> FofX_3,
	Clr_SOP_Reg => Clr_SOP_Reg,	
	Negative_Out => Negative_3
		);

DCT_parallel_4: DCT_parallel
PORT MAP (
	Clk => Clk,			
	Reset => Reset,
	Reg_En	=> Reg_En,			
	Mux_OUT	=> mux_sig_out,			
	--input for the cos_mux1
	 cos_1 => cos25,
	 cos_2 => cos26,
	 cos_3 => cos27,
	 cos_4 => cos28,
	 cos_5 => cos29,
	 cos_6 => cos30,
	 cos_7 => cos31,
	 cos_8 => cos32,
	Cos_Mux_Sel	=> Cos_Mux_Sel,
	Mult_Reg_En => Mult_Reg_En,
	Neg_Reg_En	=> Neg_Reg_En_4,
	Mult_Sel 	=> Mult_Sel_4,
	SOP_Reg_En	=> SOP_Reg_En,
	Output_Sel => Output_Sel_4,
	FofX_Out 	=> FofX_4,
	Clr_SOP_Reg => Clr_SOP_Reg,	
	Negative_Out => Negative_4	
		);

DCT_parallel_5: DCT_parallel
PORT MAP (
	Clk => Clk,			
	Reset => Reset,
	Reg_En	=> Reg_En,			
	Mux_OUT	=> mux_sig_out,			
	--input for the cos_mux1
	 cos_1 => cos33,
	 cos_2 => cos34,
	 cos_3 => cos35,
	 cos_4 => cos36,
	 cos_5 => cos37,
	 cos_6 => cos38,
	 cos_7 => cos39,
	 cos_8 => cos40,
	Cos_Mux_Sel	=> Cos_Mux_Sel,
	Mult_Reg_En => Mult_Reg_En,
	Neg_Reg_En	=> Neg_Reg_En_5,
	Mult_Sel 	=> Mult_Sel_5,
	SOP_Reg_En	=> SOP_Reg_En,
	Output_Sel => Output_Sel_5,
	FofX_Out 	=> FofX_5,
	Clr_SOP_Reg => Clr_SOP_Reg,	
	Negative_Out => Negative_5	
		);

DCT_parallel_6: DCT_parallel
PORT MAP (
	Clk => Clk,			
	Reset => Reset,
	Reg_En	=> Reg_En,			
	Mux_OUT	=> mux_sig_out,			
	--input for the cos_mux1
	 cos_1 => cos41,
	 cos_2 => cos42,
	 cos_3 => cos43,
	 cos_4 => cos44,
	 cos_5 => cos45,
	 cos_6 => cos46,
	 cos_7 => cos47,
	 cos_8 => cos48,
	Cos_Mux_Sel	=> Cos_Mux_Sel,
	Mult_Reg_En => Mult_Reg_En,
	Neg_Reg_En	=> Neg_Reg_En_6,
	Mult_Sel 	=> Mult_Sel_6,
	SOP_Reg_En	=> SOP_Reg_En,
	Output_Sel => Output_Sel_6,
	FofX_Out 	=> FofX_6,
	Clr_SOP_Reg => Clr_SOP_Reg,	
	Negative_Out => Negative_6
		);

DCT_parallel_7: DCT_parallel
PORT MAP (
	Clk => Clk,			
	Reset => Reset,
	Reg_En	=> Reg_En,			
	Mux_OUT	=> mux_sig_out,			
	--input for the cos_mux1
	 cos_1 => cos49,
	 cos_2 => cos50,
	 cos_3 => cos51,
	 cos_4 => cos52,
	 cos_5 => cos53,
	 cos_6 => cos54,
	 cos_7 => cos55,
	 cos_8 => cos56,
	Cos_Mux_Sel	=> Cos_Mux_Sel,
	Mult_Reg_En => Mult_Reg_En,
	Neg_Reg_En	=> Neg_Reg_En_7,
	Mult_Sel 	=> Mult_Sel_7,
	SOP_Reg_En	=> SOP_Reg_En,
	Output_Sel => Output_Sel_7,
	FofX_Out 	=> FofX_7,
	Clr_SOP_Reg => Clr_SOP_Reg,	
	Negative_Out => Negative_7
		);

DCT_parallel_8: DCT_parallel
PORT MAP (
	Clk => Clk,			
	Reset => Reset,
	Reg_En	=> Reg_En,			
	Mux_OUT	=> mux_sig_out,			
	--input for the cos_mux1
	 cos_1 => cos57,
	 cos_2 => cos58,
	 cos_3 => cos59,
	 cos_4 => cos60,
	 cos_5 => cos61,
	 cos_6 => cos62,
	 cos_7 => cos63,
	 cos_8 => cos64,
	Cos_Mux_Sel	=> Cos_Mux_Sel,
	Mult_Reg_En => Mult_Reg_En,
	Neg_Reg_En	=> Neg_Reg_En_8,
	Mult_Sel 	=> Mult_Sel_8,
	SOP_Reg_En	=> SOP_Reg_En,
	Output_Sel => Output_Sel_8,
	Fofx_Out 	=> FofX_8,
	Clr_SOP_Reg => Clr_SOP_Reg,	
	Negative_Out => Negative_8
		);

end DCT_Parallel_Main1_arch;