-- IEEE Library
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

ENTITY DCT_parallel IS
--generic value for the number of bits ofr the input and the output
generic (n: integer := 16;
		m: integer:= 36);
PORT(

	Clk					: IN	STD_LOGIC;		-- Global Clk
	Reset				: IN	STD_LOGIC;		-- Global Reset
	--from the controller
	Reg_En				: IN	STD_LOGIC;		--enable for the reg to DCT_Calc
	--output from DCT_Fofx as an input 	
	Mux_OUT				: IN STD_LOGIC_VECTOR (n-1 downto 0);
	--input for the cos_mux
	cos_1		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	cos_2		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	cos_3		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	cos_4		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	cos_5		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	cos_6		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	cos_7		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	cos_8		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	--MUX to select the values for cos_mux 
	Cos_Mux_Sel	:IN STD_LOGIC_VECTOR (2 downto 0); --from controller
	--in for the DCT_Calc
	--from the controller
	Mult_Reg_En: IN STD_LOGIC; --Signals related to Mult_Reg
	Neg_Reg_En: IN STD_LOGIC; --Signals related to Neg_Reg
	Mult_Sel: IN STD_LOGIC;
	SOP_Reg_En: IN STD_LOGIC;
	Output_Sel: IN STD_LOGIC;
	Clr_SOP_Reg: IN STD_LOGIC;
	--out of the DCT_main
	FofX_Out 			: OUT STD_LOGIC_VECTOR (m-1 downto 0); -- F(u) output
	Negative_Out			: OUT STD_LOGIC;
	--debug
	Reg1_Out			: OUT STD_LOGIC_VECTOR (n-1 downto 0); --output of Reg1
	Reg2_Out			: OUT STD_LOGIC_VECTOR (n-1 downto 0) --output of Reg2	
		);
END DCT_parallel;

architecture DCT_parallel_arch of DCT_parallel is
	-- signals i.e the output of the Reg
	signal  cos_out_sig		 : STD_LOGIC_VECTOR (n-1 downto 0):= (others => '0'); --input to Reg1
	signal  reg1_out_sig	 : STD_LOGIC_VECTOR (n-1 downto 0):= (others => '0');
	signal  reg2_out_sig	 : STD_LOGIC_VECTOR (n-1 downto 0):= (others => '0');

--Component declaration of DCT_Reg
COMPONENT DCT_Calc
PORT(
	Clk: IN	STD_LOGIC;		-- Global Clk
	Reset: IN STD_LOGIC;	-- Global Reset

	--Inputs to the Calculator unit
	fx: IN STD_LOGIC_VECTOR(n-1 downto 0);
	Cos: IN STD_LOGIC_VECTOR(n-1 downto 0);
	
	--Outputs of the Calculator Unit
	FofX : OUT STD_LOGIC_VECTOR(m-1 downto 0);
	Negative: OUT STD_LOGIC;

	--Inputs from Controller
	Mult_Reg_En: IN STD_LOGIC;--Signals related to Mult_Reg
	Neg_Reg_En: IN STD_LOGIC;--Signals related to Neg_Reg
	Mult_Sel: IN STD_LOGIC;
	SOP_Reg_En: IN STD_LOGIC;
	Output_Sel: IN STD_LOGIC;
	Clr_SOP_Reg: IN STD_LOGIC
	);
END COMPONENT;

COMPONENT DCT_Reg
PORT(
		Reg_In		: IN	STD_LOGIC_VECTOR(n-1 downto 0);
		Clk			: IN	STD_LOGIC;
		Reset		: IN	STD_LOGIC;
		Reg_En		: IN	STD_LOGIC;
		Reg_Out		: OUT 	STD_LOGIC_VECTOR(n-1 downto 0) 
	);
END COMPONENT;

begin
--Portmap registers
DCT_REG1:DCT_Reg  --register for output from DCT_Fofx
	PORT MAP (
		Reg_In => Mux_OUT,
		Reg_Out => reg1_out_sig,
		Reset => Reset,
		Reg_En => Reg_En,
		Clk => Clk
		);
DCT_REG2:DCT_Reg --register for DCT_cos
	PORT MAP (
		Reg_In => cos_out_sig,
		Reg_Out => reg2_out_sig,
		Reset => Reset,
		Reg_En => Reg_En,
		Clk => Clk
		);
--portmap for the DCT_Calc
DCT_CALC_1: DCT_Calc
PORT MAP (
	Clk => Clk,			
	Reset => Reset,
	--Inputs to the Calculator unit
	fx => reg1_out_sig,
	Cos => reg2_out_sig,
	--Outputs of the Calculator Unit
	FofX => FofX_Out,
	Negative=> Negative_Out,
	--Inputs from Controller
	Mult_Reg_En => Mult_Reg_En,
	Neg_Reg_En => Neg_Reg_En,
	Mult_Sel => Mult_Sel, 
	SOP_Reg_En => SOP_Reg_En,
	Output_Sel => Output_Sel,
	Clr_SOP_Reg => Clr_SOP_Reg
	);
--debug
Reg1_Out <= reg1_out_sig;
Reg2_Out <= reg2_out_sig;
process(Cos_Mux_Sel, cos_1, cos_2, cos_3, cos_4, cos_5, cos_6, cos_7, cos_8 )
begin
case Cos_Mux_Sel is
	when "000" =>
		cos_out_sig <= cos_1;
			
	when "001" =>
		cos_out_sig <= cos_2;
		
	when "010" =>
		cos_out_sig <= cos_3;
				
	when "011" =>
		cos_out_sig <= cos_4;
				
	when "100" =>
		cos_out_sig <= cos_5;
				
	when "101" =>
		cos_out_sig <= cos_6;
				
	when "110" =>
		cos_out_sig <= cos_7;
				
	when "111" =>
		cos_out_sig <= cos_8;
		
	when others => 
		cos_out_sig <= (others => '0');

end case;
end process;
end DCT_parallel_arch;