-- IEEE Library
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity DCT_parallel_TOP is
--generic parameters
generic (n: integer := 16;
	m: integer:= 36);
port(
	-- Global System Inputs
	Clk: IN	STD_LOGIC;	-- Global Clk
	Reset: IN STD_LOGIC;	-- Global Reset

	--Inputs
	Start: IN STD_LOGIC;
	fx1: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx2: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx3: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx4: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx5: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx6: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx7: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx8: IN STD_LOGIC_VECTOR (n-1 downto 0);
	
	--outputs
	FofX_1:Out STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_2:OUT STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_3:Out STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_4:OUT STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_5:Out STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_6:OUT STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_7:Out STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_8:OUT STD_LOGIC_VECTOR (m-1 downto 0);
	--Outputs
--	FofX_Done: OUT STD_LOGIC;
	Done: OUT STD_LOGIC
	);
end DCT_parallel_TOP;

architecture DCT_parallel_TOP_arch of DCT_parallel_TOP is

--Signals associated with DCT_Controller
signal Reg1_En: STD_LOGIC_VECTOR (7 downto 0);
signal Mux1_En: STD_LOGIC_VECTOR (2 downto 0);
signal Reg2_En: STD_LOGIC;

signal Negative_1:  STD_LOGIC;
signal Negative_2:  STD_LOGIC;
signal Negative_3:  STD_LOGIC;
signal Negative_4:  STD_LOGIC;
signal Negative_5:  STD_LOGIC;
signal Negative_6:  STD_LOGIC;
signal Negative_7:  STD_LOGIC;
signal Negative_8:  STD_LOGIC;

signal Neg_Reg_En_1:  STD_LOGIC; 
signal Neg_Reg_En_2:  STD_LOGIC;
signal Neg_Reg_En_3:  STD_LOGIC;
signal Neg_Reg_En_4:  STD_LOGIC;
signal Neg_Reg_En_5:  STD_LOGIC; 
signal Neg_Reg_En_6:  STD_LOGIC;
signal Neg_Reg_En_7:  STD_LOGIC;
signal Neg_Reg_En_8:  STD_LOGIC;

signal Mult_Reg_En: STD_LOGIC;

signal Mult_Sel_1: STD_LOGIC;
signal Mult_Sel_2: STD_LOGIC;
signal Mult_Sel_3: STD_LOGIC;
signal Mult_Sel_4: STD_LOGIC;
signal Mult_Sel_5: STD_LOGIC;
signal Mult_Sel_6: STD_LOGIC;
signal Mult_Sel_7: STD_LOGIC;
signal Mult_Sel_8: STD_LOGIC;

signal SOP_Reg_En: STD_LOGIC;

signal Output_Sel_1:  STD_LOGIC;
signal Output_Sel_2:  STD_LOGIC;
signal Output_Sel_3:  STD_LOGIC;
signal Output_Sel_4:  STD_LOGIC;
signal Output_Sel_5:  STD_LOGIC;
signal Output_Sel_6:  STD_LOGIC;
signal Output_Sel_7:  STD_LOGIC;
signal Output_Sel_8:  STD_LOGIC;

signal Clr_SOP_Reg: STD_LOGIC;
signal Cos_Mux_Sel	: STD_LOGIC_VECTOR (2 downto 0);

component DCT_Parallel_Main1
port(
	Clk: IN	STD_LOGIC;		-- Global Clk
	Reset: IN STD_LOGIC;		-- Global Reset
	--from the controller
	Reg_En: IN STD_LOGIC;		--enable for the reg to DCT_Calc
	--output from DCT_Fofx as an input 
		
	--for the DCT_Fofx 
	Cont_Reg_En:IN STD_LOGIC_VECTOR (7 downto 0);
	Cont_MUX_Enable:IN STD_LOGIC_VECTOR (2 downto 0);
	
	fx1:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx2:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx3:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx4:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx5:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx6:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx7:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx8:IN STD_LOGIC_VECTOR (n-1 downto 0);
	--for DCT_parallel 
	Cos_Mux_Sel	:IN STD_LOGIC_VECTOR (2 downto 0); --from controller
	--in for the DCT_Calc
	--from the controller
	Mult_Reg_En: IN STD_LOGIC; --Signals related to Mult_Reg
	
	Neg_Reg_En_1: IN STD_LOGIC; 
	Neg_Reg_En_2: IN STD_LOGIC;
	Neg_Reg_En_3: IN STD_LOGIC;
	Neg_Reg_En_4: IN STD_LOGIC;
	Neg_Reg_En_5: IN STD_LOGIC; 
	Neg_Reg_En_6: IN STD_LOGIC;
	Neg_Reg_En_7: IN STD_LOGIC;
	Neg_Reg_En_8: IN STD_LOGIC;
	
	Mult_Sel_1: IN STD_LOGIC;
	Mult_Sel_2: IN STD_LOGIC;
	Mult_Sel_3: IN STD_LOGIC;
	Mult_Sel_4: IN STD_LOGIC;
	Mult_Sel_5: IN STD_LOGIC;
	Mult_Sel_6: IN STD_LOGIC;
	Mult_Sel_7: IN STD_LOGIC;
	Mult_Sel_8: IN STD_LOGIC;
	SOP_Reg_En: IN STD_LOGIC;
	
	--output select
	Output_Sel_1: IN STD_LOGIC;
	Output_Sel_2: IN STD_LOGIC;
	Output_Sel_3: IN STD_LOGIC;
	Output_Sel_4: IN STD_LOGIC;
	Output_Sel_5: IN STD_LOGIC;
	Output_Sel_6: IN STD_LOGIC;
	Output_Sel_7: IN STD_LOGIC;
	Output_Sel_8: IN STD_LOGIC;
	
	--out of the DCT_main
	Negative_1: OUT STD_LOGIC;
	Negative_2: OUT STD_LOGIC;
	Negative_3: OUT STD_LOGIC;
	Negative_4: OUT STD_LOGIC;
	Negative_5: OUT STD_LOGIC;
	Negative_6: OUT STD_LOGIC;
	Negative_7: OUT STD_LOGIC;
	Negative_8: OUT STD_LOGIC;
	
	FofX_1:Out STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_2:OUT STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_3:Out STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_4:OUT STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_5:Out STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_6:OUT STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_7:Out STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_8:OUT STD_LOGIC_VECTOR (m-1 downto 0);
	Clr_SOP_Reg: IN STD_LOGIC
	
	);
end component;

component DCT_Parallel_Controller
port(
	-- Global System Inputs
	Clk: IN	STD_LOGIC;		-- Global Clk
	Reset: IN	STD_LOGIC;	-- Global Reset
		
	--Inputs from the Main module
	Start: IN STD_LOGIC;

	--Output to the Main Module
	Done: OUT STD_LOGIC;
	
	-- Outputs to DCT_Cos
	Cos_Mux_Sel: OUT STD_LOGIC_VECTOR (2 downto 0);

	--Outputs to DCT_Cos and DCT_fofx
	Mux1_En: OUT STD_LOGIC_VECTOR (2 downto 0);
	Reg1_En: OUT STD_LOGIC_VECTOR (7 downto 0);

	--Outputs to Register that store f(x) and Cos(x)
	Reg2_En: OUT STD_LOGIC;

	--Inputs from DCT_Calc
	Negative1: IN STD_LOGIC;
	Negative2: IN STD_LOGIC;
	Negative3: IN STD_LOGIC;
	Negative4: IN STD_LOGIC;
	Negative5: IN STD_LOGIC;
	Negative6: IN STD_LOGIC;
	Negative7: IN STD_LOGIC;
	Negative8: IN STD_LOGIC;

	--Outputs to DCT_Calc
	Neg_Reg_En1: OUT STD_LOGIC; 
	Neg_Reg_En2: OUT STD_LOGIC;
	Neg_Reg_En3: OUT STD_LOGIC;
	Neg_Reg_En4: OUT STD_LOGIC;
	Neg_Reg_En5: OUT STD_LOGIC; 
	Neg_Reg_En6: OUT STD_LOGIC;
	Neg_Reg_En7: OUT STD_LOGIC;
	Neg_Reg_En8: OUT STD_LOGIC;

	Mult_Reg_En: OUT STD_LOGIC;	--Enable signal for Mult_Reg

	Mult_Sel1: OUT STD_LOGIC;
	Mult_Sel2: OUT STD_LOGIC;
	Mult_Sel3: OUT STD_LOGIC;
	Mult_Sel4: OUT STD_LOGIC;
	Mult_Sel5: OUT STD_LOGIC;
	Mult_Sel6: OUT STD_LOGIC;
	Mult_Sel7: OUT STD_LOGIC;
	Mult_Sel8: OUT STD_LOGIC;	
	
	SOP_Reg_En: OUT STD_LOGIC;	--Enable signal for SOP_Reg

	Output_Sel1: OUT STD_LOGIC;
	Output_Sel2: OUT STD_LOGIC;
	Output_Sel3: OUT STD_LOGIC;
	Output_Sel4: OUT STD_LOGIC;
	Output_Sel5: OUT STD_LOGIC;
	Output_Sel6: OUT STD_LOGIC;
	Output_Sel7: OUT STD_LOGIC;
	Output_Sel8: OUT STD_LOGIC;
	
	Clr_SOP_Reg: OUT STD_LOGIC
	);
end component;

begin

--debug

--DCT_main
DCT: DCT_Parallel_Main1
port map(
	
	--Global Inputs
	Clk => Clk,
	Reset => Reset,
	
	--DCT_Fofx
	--Inputs from the Controller
	Reg_En => Reg2_En,
	
	--Inputs 
	fx1 => fx1,
	fx2 => fx2,
	fx3 => fx3,
	fx4 => fx4,
	fx5 => fx5,
	fx6 => fx6,
	fx7 => fx7,
	fx8 => fx8,

	--DCT_cos
	--Inputs from the Controller
	Cont_Reg_En => Reg1_En,
	Cont_MUX_Enable => Mux1_En,
	--DCT_Calc
	--Inputs from the controller
	Mult_Reg_En => Mult_Reg_En,
	Neg_Reg_En_1 => Neg_Reg_En_1,
	Neg_Reg_En_2 => Neg_Reg_En_2,
	Neg_Reg_En_3 => Neg_Reg_En_3,
	Neg_Reg_En_4 => Neg_Reg_En_4,
	Neg_Reg_En_5 => Neg_Reg_En_5, 
	Neg_Reg_En_6 => Neg_Reg_En_6,
	Neg_Reg_En_7 => Neg_Reg_En_7,
	Neg_Reg_En_8 => Neg_Reg_En_8,
	Mult_Sel_1 => Mult_Sel_1,
	Mult_Sel_2 => Mult_Sel_2,
	Mult_Sel_3 => Mult_Sel_3,
	Mult_Sel_4 => Mult_Sel_4,
	Mult_Sel_5 => Mult_Sel_5,
	Mult_Sel_6 => Mult_Sel_6,
	Mult_Sel_7 => Mult_Sel_7,
	Mult_Sel_8 => Mult_Sel_8,
	SOP_Reg_En => SOP_Reg_En,
	Output_Sel_1=>Output_Sel_1,
	Output_Sel_2=>Output_Sel_2,
	Output_Sel_3=>Output_Sel_3,
	Output_Sel_4=>Output_Sel_4,
	Output_Sel_5=>Output_Sel_5,
	Output_Sel_6=>Output_Sel_6,
	Output_Sel_7=>Output_Sel_7,
	Output_Sel_8=>Output_Sel_8,
	Clr_SOP_Reg => Clr_SOP_Reg,
	Cos_Mux_Sel=>Cos_Mux_Sel,
	--Output
	Negative_1 => Negative_1,
	Negative_2 => Negative_2,
	Negative_3 => Negative_3,
	Negative_4 => Negative_4,
	Negative_5 => Negative_5,
	Negative_6 => Negative_6,
	Negative_7 => Negative_7,
	Negative_8 => Negative_8,
	FofX_1 => FofX_1,		
	FofX_2 => FofX_2,		
	FofX_3 => FofX_3,		
	FofX_4 => FofX_4,		
	FofX_5 => FofX_5,		
	FofX_6 => FofX_6,		
	FofX_7 => FofX_7,
	FofX_8 => FofX_8
	);

--Controller
Controller: DCT_Parallel_Controller
port map(
	
	 -- Global System Inputs
	Clk => Clk,
	Reset => Reset,
		
	--Inputs from the Main module
	Start => Start,

	--Output to the Main Module
	--FofX_Done => FofX_Done,
	Done => Done,
	
	-- Outputs to DCT_Cos
	Cos_Mux_Sel=>Cos_Mux_Sel,
	--Outputs to DCT_Cos and DCT_fofx
	Mux1_En => Mux1_En,
	Reg1_En => Reg1_En,

	--Outputs to Register that store f(x) and Cos(x)
	Reg2_En => Reg2_En,

	--Inputs from DCT_Calc
	Negative1 => Negative_1,
	Negative2 => Negative_2,
	Negative3 => Negative_3,
	Negative4 => Negative_4,
	Negative5 => Negative_5,
	Negative6 => Negative_6,
	Negative7 => Negative_7,
	Negative8 => Negative_8,

	--Outputs to DCT_Calc
	Neg_Reg_En1 => Neg_Reg_En_1,
	Neg_Reg_En2 => Neg_Reg_En_2,
	Neg_Reg_En3 => Neg_Reg_En_3,
	Neg_Reg_En4 => Neg_Reg_En_4,
	Neg_Reg_En5 => Neg_Reg_En_5, 
	Neg_Reg_En6 => Neg_Reg_En_6,
	Neg_Reg_En7 => Neg_Reg_En_7,
	Neg_Reg_En8 => Neg_Reg_En_8,
	
	Mult_Reg_En => Mult_Reg_En,
	
	Mult_Sel1 => Mult_Sel_1,
	Mult_Sel2 => Mult_Sel_2,
	Mult_Sel3 => Mult_Sel_3,
	Mult_Sel4 => Mult_Sel_4,
	Mult_Sel5 => Mult_Sel_5,
	Mult_Sel6 => Mult_Sel_6,
	Mult_Sel7 => Mult_Sel_7,
	Mult_Sel8 => Mult_Sel_8,
	
	SOP_Reg_En => SOP_Reg_En,
	
	Output_Sel1=>Output_Sel_1,
	Output_Sel2=>Output_Sel_2,
	Output_Sel3=>Output_Sel_3,
	Output_Sel4=>Output_Sel_4,
	Output_Sel5=>Output_Sel_5,
	Output_Sel6=>Output_Sel_6,
	Output_Sel7=>Output_Sel_7,
	Output_Sel8=>Output_Sel_8
	);	
	
end DCT_parallel_TOP_arch;