library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
        
entity DCT_parallel_top_TB is
generic (n: integer := 16;
	m: integer:= 36;
	CLK_PERIOD: integer:= 100);

end DCT_parallel_top_TB; 

architecture DCT_parallel_top_TB_arch of DCT_parallel_top_TB is

component DCT_parallel_TOP
--Generic parameters
--generic (n: integer := 16;
--	m: integer:= 36);
port(
	-- Global System Inputs
	Clk: IN	STD_LOGIC;	-- Global Clk
	Reset: IN STD_LOGIC;	-- Global Reset

	--Inputs
	Start: IN STD_LOGIC;
	
	fx1: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx2: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx3: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx4: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx5: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx6: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx7: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx8: IN STD_LOGIC_VECTOR (n-1 downto 0);
	
	--outputs
	FofX_1:Out STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_2:OUT STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_3:Out STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_4:OUT STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_5:Out STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_6:OUT STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_7:Out STD_LOGIC_VECTOR (m-1 downto 0);
	FofX_8:OUT STD_LOGIC_VECTOR (m-1 downto 0);
	--Outputs
--	FofX_Done: OUT STD_LOGIC;
	Done: OUT STD_LOGIC
	);
end component;

--Signals representing ports that will be shown in simulator
signal Clk: STD_LOGIC;	-- Global Clk
signal Reset: STD_LOGIC;	-- Global Reset
signal Start: STD_LOGIC;
signal fx1: STD_LOGIC_VECTOR (n-1 downto 0);
signal fx2: STD_LOGIC_VECTOR (n-1 downto 0);
signal fx3: STD_LOGIC_VECTOR (n-1 downto 0);
signal fx4: STD_LOGIC_VECTOR (n-1 downto 0);
signal fx5: STD_LOGIC_VECTOR (n-1 downto 0);
signal fx6: STD_LOGIC_VECTOR (n-1 downto 0);
signal fx7: STD_LOGIC_VECTOR (n-1 downto 0);
signal fx8: STD_LOGIC_VECTOR (n-1 downto 0);
signal Done: STD_LOGIC;
signal FofX_1: STD_LOGIC_VECTOR (m-1 downto 0);
signal FofX_2: STD_LOGIC_VECTOR (m-1 downto 0);
signal FofX_3: STD_LOGIC_VECTOR (m-1 downto 0);
signal FofX_4: STD_LOGIC_VECTOR (m-1 downto 0);
signal FofX_5: STD_LOGIC_VECTOR (m-1 downto 0);
signal FofX_6: STD_LOGIC_VECTOR (m-1 downto 0);
signal FofX_7: STD_LOGIC_VECTOR (m-1 downto 0);
signal FofX_8: STD_LOGIC_VECTOR (m-1 downto 0);
--Clock period
--constant CLK_PERIOD: integer:= 100;

begin

--Simulating Clock
CLK_UNIT: process
begin
	loop
		clk <= '0';
		wait for 50 ns;
		clk <= not clk;
		wait for 50 ns;
	end loop;
end process;

RST_UNIT: process
begin
	Reset <= '1';
	wait for 200 ns;
	Reset <= '0';
	wait;
end process;

DCT_parallel_Inst: DCT_parallel_TOP
port map(
	-- Global System Inputs
	Clk => Clk,
	Reset => Reset,

	--Inputs
	Start => Start,
	fx1 => fx1,
	fx2 => fx2,
	fx3 => fx3,
	fx4 => fx4,
	fx5 => fx5,
	fx6 => fx6,
	fx7 => fx7,
	fx8 => fx8,

	--Outputs
	Done => Done,
	FofX_1 => FofX_1,		
	FofX_2 => FofX_2,		
	FofX_3 => FofX_3,		
	FofX_4 => FofX_4,		
	FofX_5 => FofX_5,		
	FofX_6 => FofX_6,		
	FofX_7 => FofX_7,
	FofX_8 => FofX_8
	);

process
begin
	--Initial Reset
	---------------
--	Reset <= '1';	
--	wait for 100 ns;

	--Start the DCT machine
	-----------------------
	Start <= '0';
	wait for 100 ns;
	Start <= '1';
	wait for 300 ns;
	Start <= '0';
	wait;
end process;

process
begin	
	--Inputs f(x)
	-----------------------
	fx1 <= "0000010100000000";
	fx2 <= "0000101000000000";
	fx3 <= "0000111100000000";
	fx4 <= "0001010000000000";
	fx5 <= "0001100100000000";
	fx6 <= "0001111000000000";
	fx7 <= "0010001100000000";
	fx8 <= "0010100000000000";
	wait for 100 ns;
end process;

end DCT_parallel_top_TB_arch;