------------------------------------------------------------------
--                             Controller_SM					--
-- File Name: Controller_SM.Vhd									--
-- Author: Kamesh Ramani.										--
-- Function : This is the state machine part of the controller  --
-- Created: 													--
-- Last Updated on: 4/19/03										--
------------------------------------------------------------------

-- IEEE Library
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

ENTITY Controller_SM IS
--Generic parameters
generic (n: integer := 16;		-- Number of bits of input data
		m: integer := 36);		-- Number of bits of output data
PORT(

	-- Global System Inputs
	Clk: IN	STD_LOGIC;		-- Global Clk
	Reset: IN	STD_LOGIC;	-- Global Reset
		
	--Inputs from the Main module
	Start: IN STD_LOGIC;

	--Output to the Main Module
	FofX_Done: OUT STD_LOGIC;
	Done: OUT STD_LOGIC;
	
	-- Outputs to DCT_Cos
	Cos_Mux2_En: OUT STD_LOGIC_VECTOR (2 downto 0);

	--Outputs to DCT_Cos and DCT_fofx
	Mux1_En: OUT STD_LOGIC_VECTOR (2 downto 0);
	Reg1_En: OUT STD_LOGIC_VECTOR (7 downto 0);

	--Outputs to Register that store f(x) and Cos(x)
	Reg2_En: OUT STD_LOGIC;

	--Inputs from DCT_Calc
	Negative: IN STD_LOGIC;

	--Outputs to DCT_Calc
	Neg_Reg_En: OUT STD_LOGIC;	--Enable signal for Neg_Reg
	Mult_Reg_En: OUT STD_LOGIC;	--Enable signal for Mult_Reg
	Mult_Sel: OUT STD_LOGIC;	--Signal that selects between Prod and its 2's comp
	SOP_Reg_En: OUT STD_LOGIC;	--Enable signal for SOP_Reg
	Output_Sel: OUT STD_LOGIC;	--Signal to select the output for x=0 and otherwise
	Clr_SOP_Reg: OUT STD_LOGIC
	);
END Controller_SM;

architecture Control1er_SM_arch of Controller_SM is

--Signals related to Count_Eight_1
signal Count_Eight_1, Cnt_Eight_1: STD_LOGIC_VECTOR(2 downto 0);
signal Clr_Cnt_Eight_1, Inc_Cnt_Eight_1:STD_LOGIC;

--Signals related to Count_Eight_2
signal Count_Eight_2, Cnt_Eight_2: STD_LOGIC_VECTOR(2 downto 0);
signal Clr_Cnt_Eight_2, Inc_Cnt_Eight_2:STD_LOGIC;

--Signals related to Detect_x0
signal Zero: STD_LOGIC;

-- Controller FSM states
type STATE_TYPE is (Idle, Cos_Select, Register_Select, Mux_Select, Store_Inputs, Store_Neg, Store_Mult, Select_Mult, Store_SOP, Select_Output);
signal CurrentState, NextState: STATE_TYPE;

begin

-- Debug 

-- Controller FSM
State_machine: process(CurrentState, Start, Cnt_Eight_1, Cnt_Eight_2, Negative)
begin

-- Default all outputs to FALSE
Inc_Cnt_Eight_1 <= '0'; Clr_Cnt_Eight_1 <= '0';
Inc_Cnt_Eight_2 <= '0'; Clr_Cnt_Eight_2 <= '0';
Done <= '0';
Cos_Mux2_En <= "000";
Mux1_En <= "000"; Reg1_En <= "00000000";
Reg2_En <= '0';
Neg_Reg_En <= '0'; Mult_Reg_En <= '0'; Mult_Sel <= '0'; SOP_Reg_En <= '0'; Clr_SOP_Reg <= '0';
FofX_Done <= '0';

case CurrentState is

	when Idle =>
		if (Start = '1') then
			NextState <= Cos_Select;
		else
			NextState <= Idle;
		end if;
	
	when Cos_Select =>
		Cos_Mux2_En <= Cnt_Eight_1;
		NextState <= Register_Select;
	
	when Register_Select =>
--		Inc_Cnt_Eight_1 <= '1';
		Cos_Mux2_En <= Cnt_Eight_1;
		Reg1_En <= "11111111";
		NextState <= Mux_Select;

	when Mux_Select =>
		Mux1_En <= Cnt_Eight_2;
		NextState <= Store_Inputs;

	when Store_Inputs =>
--		Inc_Cnt_Eight_2 <= '1';
		Mux1_En <= Cnt_Eight_2;
		Reg2_En <= '1';
		NextState <= Store_Neg;

	when Store_Neg =>
		Neg_Reg_En <= '1';
		NextState <= Store_Mult;

	when Store_Mult =>
		Mult_Reg_En <= '1';
		NextState <= Select_Mult;

	when Select_Mult =>
		if (Negative = '1') then
			Mult_Sel <= '1';
		else
			Mult_Sel <= '0';
		end if;
		NextState <= Store_SOP;

	when Store_SOP =>
		if (Negative = '1') then
			Mult_Sel <= '1';
		else
			Mult_Sel <= '0';
		end if;
		SOP_Reg_En <= '1';
		NextState <= Select_Output;

	when Select_Output =>
		if (Cnt_Eight_1 = "000") then
			Zero <= '1';
		else
			Zero <= '0';
		end if;
		if (Cnt_Eight_1 = "111") then
			if (Cnt_Eight_2 ="111") then
				Clr_Cnt_Eight_1 <= '1';
				Clr_Cnt_Eight_2 <= '1';
				FofX_Done <= '1';
				Done <= '1';
				NextState <= Idle;
			else
				FofX_Done <= '0';
				Inc_Cnt_Eight_2 <= '1';
				NextState <= Mux_Select;
			end if;
		elsif (Cnt_Eight_2 = "111") then
			Clr_Cnt_Eight_2 <= '1';
			Inc_Cnt_Eight_1 <= '1';
			FofX_Done <= '1';
			Clr_SOP_Reg <= '1';
			NextState <= Cos_Select;
		else
			FofX_Done <= '0';
			Clr_SOP_Reg <= '0';
			Inc_Cnt_Eight_2 <= '1';
			NextState <= Mux_Select;
		end if;		
	when others =>
		NextState <= Idle;

end case;

end process;

-- To synchorinize the statemachine with Global Clk
State_Sync:process (Clk, Reset)
begin
    if (Reset='1') then
        CurrentState <= Idle;
    elsif (Clk'event and Clk = '1') then
        CurrentState <= NextState;
	end if;
end process;

-- Counter for player's turn
Counter_Eight_1:process (Clk, Reset)
begin
    if (Reset='1') then
        Count_Eight_1 <= "000";
    elsif (Clk'event and Clk = '1') then
		if (Clr_Cnt_Eight_1 = '1') then
			Count_Eight_1 <= "000";
		elsif (Inc_Cnt_Eight_1 = '1') then
			Count_Eight_1 <= Count_Eight_1 + "001";
		end if;
    end if;
end process;
Cnt_Eight_1 <= Count_Eight_1;

Counter_Eight_2:process (Clk, Reset)
begin
    if (Reset='1') then
        Count_Eight_2 <= "000";
    elsif (Clk'event and Clk = '1') then
		if (Clr_Cnt_Eight_2 = '1') then
			Count_Eight_2 <= "000";
		elsif (Inc_Cnt_Eight_2 = '1') then
			Count_Eight_2 <= Count_Eight_2 + "001";
		end if;
    end if;
end process;
Cnt_Eight_2 <= Count_Eight_2;

--Process to detect x = 0;
Detect_x0: process (Clk, Reset, Zero)
begin
    if (Reset='1') then
        Output_Sel <= '0';
    elsif (Clk'event and Clk = '1') then
		if (Zero = '1') then
	        Output_Sel <= '1';
		else
			Output_Sel <= '0';
		end if;
	end if;
end process;

end Control1er_SM_arch;