LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY DCT_Reg IS
--generic value for the number of bits ofr the input and the output
generic (n:integer :=16); --no of bits

	PORT
	(
		Reg_In		: IN	STD_LOGIC_VECTOR(n-1 downto 0);
		Clk			: IN	STD_LOGIC;
		Reset		: IN	STD_LOGIC;
		Reg_En		: IN	STD_LOGIC;
		Reg_Out		: OUT 	STD_LOGIC_VECTOR(n-1 downto 0) 
	);
	
END DCT_Reg;

ARCHITECTURE Reg OF  DCT_Reg IS

BEGIN

	PROCESS (Clk, Reset)
	BEGIN
	
		IF Reset = '1' THEN
		
			Reg_Out <= (others => '0');
			
		ELSIF (Clk'EVENT AND Clk = '1') THEN
		
			IF Reg_En = '1' THEN
			
				Reg_Out <= Reg_In;
			
			ELSE
			
				NULL ;
				
			END IF;
			
		END IF;
		
	END PROCESS;
			
END Reg;