library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
        
entity DCT_Serial_TB is
generic (n: integer := 16;
	m: integer:= 36;
	CLK_PERIOD: integer:= 100);

end DCT_Serial_TB; 

architecture DCT_Serial_TB_arch of DCT_Serial_TB is

component DCT_Serial_TOP
--Generic parameters
generic (n: integer := 16;
	m: integer:= 36);
port(
	-- Global System Inputs
	Clk: IN	STD_LOGIC;	-- Global Clk
	Reset: IN STD_LOGIC;	-- Global Reset

	--Inputs
	Start: IN STD_LOGIC;
	fx1: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx2: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx3: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx4: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx5: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx6: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx7: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx8: IN STD_LOGIC_VECTOR (n-1 downto 0);

	--Outputs
	FofX_Done: OUT STD_LOGIC;
	Done: OUT STD_LOGIC;
	FofX: OUT STD_LOGIC_VECTOR (m-1 downto 0)
	);
end component;

--Signals representing ports that will be shown in simulator
signal Clk: STD_LOGIC;	-- Global Clk
signal Reset: STD_LOGIC;	-- Global Reset
signal Start: STD_LOGIC;
signal fx1: STD_LOGIC_VECTOR (n-1 downto 0);
signal fx2: STD_LOGIC_VECTOR (n-1 downto 0);
signal fx3: STD_LOGIC_VECTOR (n-1 downto 0);
signal fx4: STD_LOGIC_VECTOR (n-1 downto 0);
signal fx5: STD_LOGIC_VECTOR (n-1 downto 0);
signal fx6: STD_LOGIC_VECTOR (n-1 downto 0);
signal fx7: STD_LOGIC_VECTOR (n-1 downto 0);
signal fx8: STD_LOGIC_VECTOR (n-1 downto 0);
signal FofX_Done: STD_LOGIC;
signal Done: STD_LOGIC;
signal FofX: STD_LOGIC_VECTOR (m-1 downto 0);

--Clock period
--constant CLK_PERIOD: integer:= 100;

begin
CLK_UNIT: process
begin
	loop
		clk <= '0';
		wait for 100 ns;
		clk <= not clk;
		wait for 100 ns;
	end loop;
end process;

RST_UNIT: process
begin
	Reset <= '1';
	wait for 400 ns;
	Reset <= '0';
	wait;
end process;

DCT_Serial_Inst: DCT_Serial_TOP
port map(
	-- Global System Inputs
	Clk => Clk,
	Reset => Reset,

	--Inputs
	Start => Start,
	fx1 => fx1,
	fx2 => fx2,
	fx3 => fx3,
	fx4 => fx4,
	fx5 => fx5,
	fx6 => fx6,
	fx7 => fx7,
	fx8 => fx8,

	--Outputs
	FofX_Done => FofX_Done,
	Done => Done,
	FofX => FofX
	);

--Simulating Clock


--	
process
begin
	--Initial Reset
	---------------
--	Reset <= '1';	
--	wait for 100 ns;

	--Start the DCT machine
	-----------------------
	Start <= '0';
	wait for 200 ns;
	Start <= '1';
	wait for 600 ns;
	Start <= '0';
	wait;
end process;

process
begin	
	--Inputs f(x)
	-----------------------
	fx1 <= "0000000010000000";
	fx2 <= "0000000100000000";
	fx3 <= "0000000110000000";
	fx4 <= "0000001000000000";
	fx5 <= "0000001010000000";
	fx6 <= "0000001100000000";
	fx7 <= "0000001110000000";
	fx8 <= "0000010000000000";
	wait for 200 ns;
end process;

end DCT_Serial_TB_arch;