-- IEEE Library
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity DCT_Serial_TOP is
--generic parameters
generic (n: integer := 16;
	m: integer:= 36);
port(
	-- Global System Inputs
	Clk: IN	STD_LOGIC;	-- Global Clk
	Reset: IN STD_LOGIC;	-- Global Reset

	--Inputs
	Start: IN STD_LOGIC;
	fx1: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx2: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx3: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx4: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx5: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx6: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx7: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx8: IN STD_LOGIC_VECTOR (n-1 downto 0);

	--Outputs
	FofX_Done: OUT STD_LOGIC;
	Done: OUT STD_LOGIC;
	FofX: OUT STD_LOGIC_VECTOR (m-1 downto 0)
	);
end DCT_Serial_TOP;

architecture DCT_Serial_TOP_arch of DCT_Serial_TOP is

--Signals associated with DCT_Controller
signal Cos_Mux2_En: STD_LOGIC_VECTOR (2 downto 0);
signal Reg1_En: STD_LOGIC_VECTOR (7 downto 0);
signal Mux1_En: STD_LOGIC_VECTOR (2 downto 0);
signal Reg2_En: STD_LOGIC;
signal Negative: STD_LOGIC;
signal Neg_Reg_En: STD_LOGIC;
signal Mult_Reg_En: STD_LOGIC;
signal Mult_Sel: STD_LOGIC;
signal SOP_Reg_En: STD_LOGIC;
signal Output_Sel: STD_LOGIC;
signal Clr_SOP_Reg: STD_LOGIC;

component DCT_main
port(
	--Global Inputs
	Clk: IN STD_LOGIC;	-- Global Clk
	Reset: IN STD_LOGIC;	-- Global Reset
	
	--DCT_Fofx
	--Inputs from the Controller
	Reg_En: IN STD_LOGIC;	--enable for the reg to DCT_Calc
	--Inputs 
	fx1: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx2: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx3: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx4: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx5: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx6: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx7: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx8: IN STD_LOGIC_VECTOR (n-1 downto 0);

	--DCT_cos
	--Inputs from the Controller
	Cont_Reg_En: IN STD_LOGIC_VECTOR (7 downto 0);
	Cont_MUX_Enable: IN STD_LOGIC_VECTOR (2 downto 0);
	Cont_MUX2_Enable: IN STD_LOGIC_VECTOR (2 downto 0);

	--DCT_Calc
	--Inputs from the controller
	Mult_Reg_En: IN STD_LOGIC; --Signals related to Mult_Reg
	Neg_Reg_En: IN STD_LOGIC; --Signals related to Neg_Reg
	Mult_Sel: IN STD_LOGIC;
	SOP_Reg_En: IN STD_LOGIC;
	Output_Sel: IN STD_LOGIC;
	Clr_SOP_Reg: IN STD_LOGIC;

	--Output
	Negative: OUT STD_LOGIC; 		
	FofX: OUT STD_LOGIC_VECTOR (m-1 downto 0) -- F(u) output
	);
end component;

component Controller_SM
port(
	-- Global System Inputs
	Clk: IN	STD_LOGIC;		-- Global Clk
	Reset: IN	STD_LOGIC;	-- Global Reset
		
	--Inputs from the Main module
	Start: IN STD_LOGIC;

	--Output to the Main Module
	FofX_Done: OUT STD_LOGIC;
	Done: OUT STD_LOGIC;
	
	-- Outputs to DCT_Cos
	Cos_Mux2_En: OUT STD_LOGIC_VECTOR (2 downto 0);

	--Outputs to DCT_Cos and DCT_fofx
	Mux1_En: OUT STD_LOGIC_VECTOR (2 downto 0);
	Reg1_En: OUT STD_LOGIC_VECTOR (7 downto 0);

	--Outputs to Register that store f(x) and Cos(x)
	Reg2_En: OUT STD_LOGIC;

	--Inputs from DCT_Calc
	Negative: IN STD_LOGIC;

	--Outputs to DCT_Calc
	Neg_Reg_En: OUT STD_LOGIC;	--Enable signal for Neg_Reg
	Mult_Reg_En: OUT STD_LOGIC;	--Enable signal for Mult_Reg
	Mult_Sel: OUT STD_LOGIC;	--Signal that selects between Prod and its 2's comp
	SOP_Reg_En: OUT STD_LOGIC;	--Enable signal for SOP_Reg
	Output_Sel: OUT STD_LOGIC;	--Signal to select the output for x=0 and otherwise
	Clr_SOP_Reg: OUT STD_LOGIC
	);
end component;

begin

--debug

--DCT_main
DCT: DCT_main
port map(
	--Global Inputs
	Clk => Clk,
	Reset => Reset,
	
	--DCT_Fofx
	--Inputs from the Controller
	Reg_En => Reg2_En,
	
	--Inputs 
	fx1 => fx1,
	fx2 => fx2,
	fx3 => fx3,
	fx4 => fx4,
	fx5 => fx5,
	fx6 => fx6,
	fx7 => fx7,
	fx8 => fx8,

	--DCT_cos
	--Inputs from the Controller
	Cont_Reg_En => Reg1_En,
	Cont_MUX_Enable => Mux1_En,
	Cont_MUX2_Enable => Cos_Mux2_En,

	--DCT_Calc
	--Inputs from the controller
	Mult_Reg_En => Mult_Reg_En,
	Neg_Reg_En => Neg_Reg_En,
	Mult_Sel => Mult_Sel,
	SOP_Reg_En => SOP_Reg_En,
	Output_Sel => Output_Sel,
	Clr_SOP_Reg => Clr_SOP_Reg,

	--Output
	Negative => Negative,
	FofX => FofX
	);

--Controller
Controller: Controller_SM
port map(
	 -- Global System Inputs
	Clk => Clk,
	Reset => Reset,
		
	--Inputs from the Main module
	Start => Start,

	--Output to the Main Module
	FofX_Done => FofX_Done,
	Done => Done,
	
	-- Outputs to DCT_Cos
	Cos_Mux2_En => Cos_Mux2_En,

	--Outputs to DCT_Cos and DCT_fofx
	Mux1_En => Mux1_En,
	Reg1_En => Reg1_En,

	--Outputs to Register that store f(x) and Cos(x)
	Reg2_En => Reg2_En,

	--Inputs from DCT_Calc
	Negative => Negative,

	--Outputs to DCT_Calc
	Neg_Reg_En => Neg_Reg_En,
	Mult_Reg_En => Mult_Reg_En,
	Mult_Sel => Mult_Sel,
	SOP_Reg_En => SOP_Reg_En,
	Output_Sel => Output_Sel,
	Clr_SOP_Reg => Clr_SOP_Reg
	);	
	
end DCT_Serial_TOP_arch;