-- IEEE Library
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

ENTITY DCT_main IS
--generic value for the number of bits ofr the input and the output
generic (n: integer := 16;
		m: integer:= 36);
PORT(
	--Global Inputs
	Clk: IN STD_LOGIC;	-- Global Clk
	Reset: IN STD_LOGIC;	-- Global Reset
	
	--DCT_Fofx
	--Inputs from the Controller
	Reg_En: IN STD_LOGIC;	--enable for the reg to DCT_Calc
	--Inputs 
	fx1: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx2: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx3: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx4: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx5: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx6: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx7: IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx8: IN STD_LOGIC_VECTOR (n-1 downto 0);

	--DCT_cos
	--Inputs from the Controller
	Cont_Reg_En: IN STD_LOGIC_VECTOR (7 downto 0);
	Cont_MUX_Enable: IN STD_LOGIC_VECTOR (2 downto 0);
	Cont_MUX2_Enable: IN STD_LOGIC_VECTOR (2 downto 0);

	--DCT_Calc
	--Inputs from the controller
	Mult_Reg_En: IN STD_LOGIC; --Signals related to Mult_Reg
	Neg_Reg_En: IN STD_LOGIC; --Signals related to Neg_Reg
	Mult_Sel: IN STD_LOGIC;
	SOP_Reg_En: IN STD_LOGIC;
	Output_Sel: IN STD_LOGIC;
	Clr_SOP_Reg: IN STD_LOGIC;

	--Output
	Negative: OUT STD_LOGIC; 		
	FofX: OUT STD_LOGIC_VECTOR (m-1 downto 0); -- F(u) output

	--debug
	Mux_OUT: OUT STD_LOGIC_VECTOR (n-1 downto 0);
	Mux2_OUT: OUT STD_LOGIC_VECTOR (n-1 downto 0)
	);
END DCT_main;

architecture DCT_main_arch of DCT_main is
	-- signals i.e the output of the Reg
	signal 	fx_sig: STD_LOGIC_VECTOR (n-1 downto 0):= (others => '0'); -- input to the multiplier
	signal  cos_sig: STD_LOGIC_VECTOR (n-1 downto 0):= (others => '0'); --input to the multiplier
	signal  mux_out_sig: STD_LOGIC_VECTOR (n-1 downto 0):= (others => '0');
	signal  mux2_out_sig: STD_LOGIC_VECTOR (n-1 downto 0):= (others => '0');
	signal  reg1_out_sig: STD_LOGIC_VECTOR (n-1 downto 0):= (others => '0');
	signal  reg2_out_sig: STD_LOGIC_VECTOR (n-1 downto 0):= (others => '0');

--Component declaration of DCT_Reg
COMPONENT DCT_Calc
PORT(
	Clk: IN	STD_LOGIC;		-- Global Clk
	Reset: IN STD_LOGIC;	-- Global Reset

	--Inputs to the Calculator unit
	fx: IN STD_LOGIC_VECTOR(n-1 downto 0);
	Cos: IN STD_LOGIC_VECTOR(n-1 downto 0);
	
	--Outputs of the Calculator Unit
	FofX: OUT STD_LOGIC_VECTOR(m-1 downto 0);
	
	--Inputs from Controller
	Neg_Reg_En: IN STD_LOGIC;--Signals related to Neg_Reg
	Mult_Reg_En: IN STD_LOGIC;--Signals related to Mult_Reg
	Mult_Sel: IN STD_LOGIC;
	SOP_Reg_En: IN STD_LOGIC;
	Output_Sel: IN STD_LOGIC;
	Clr_SOP_Reg: IN STD_LOGIC;
	
	--Outputs to the Controller
	Negative: OUT STD_LOGIC

	);
END COMPONENT;

COMPONENT DCT_Fofx
PORT(
	Clk			: IN	STD_LOGIC;		-- Global Clk
	Reset		: IN	STD_LOGIC;		-- Global Reset
	--in from the controller 
	Cont_Reg_En 	:IN STD_LOGIC_VECTOR (7 downto 0);
	Cont_MUX_Enable :IN STD_LOGIC_VECTOR (2 downto 0);
	--in to the Reg 
	fx1		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx2		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx3		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx4		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx5		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx6		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx7		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	fx8		:IN STD_LOGIC_VECTOR (n-1 downto 0);
	-- out of the mux
	Mux_OUT		: OUT STD_LOGIC_VECTOR (n-1 downto 0)
	);
END COMPONENT;

COMPONENT DCT_cos
PORT(
Clk						: IN	STD_LOGIC;		-- Global Clk
	Reset				: IN	STD_LOGIC;		-- Global Reset
	--in from the controller 
	Cont_Reg_En 		:IN STD_LOGIC_VECTOR (7 downto 0);
	Cont_MUX2_Enable	:IN STD_LOGIC_VECTOR (2 downto 0);
	Cont_MUX_Enable 	:IN STD_LOGIC_VECTOR (2 downto 0);
	--in to the Reg 
	-- out of the mux
	Mux2_OUT			: OUT STD_LOGIC_VECTOR (n-1 downto 0)
	);
END COMPONENT;

COMPONENT DCT_Reg
PORT(
		Reg_In		: IN	STD_LOGIC_VECTOR(n-1 downto 0);
		Clk			: IN	STD_LOGIC;
		Reset		: IN	STD_LOGIC;
		Reg_En		: IN	STD_LOGIC;
		Reg_Out		: OUT 	STD_LOGIC_VECTOR(n-1 downto 0) 
	);
END COMPONENT;


begin
--debug
Mux2_OUT <= mux2_out_sig;
Mux_OUT  <= mux_out_sig;

--portmap for the DCT_Fofx
DCT_Fofxp1:DCT_Fofx 
	PORT MAP (
	Clk => Clk,			
	Reset => Reset,	
	--in from the controller 
	Cont_Reg_En => Cont_Reg_En,
	Cont_MUX_Enable => Cont_MUX_Enable,
	--in to the Reg 
	fx1		=> fx1,
	fx2		=> fx2,
	fx3		=> fx3,
	fx4		=> fx4,
	fx5		=> fx5,
	fx6		=> fx6,
	fx7		=> fx7,
	fx8		=> fx8,
	-- out of the mux
	Mux_OUT	=> mux_out_sig
	);

--portmap for the DCT_cos
DCT_cos_1: DCT_cos
PORT MAP (
	Clk => Clk,			
	Reset => Reset,
	--in from the controller 
	Cont_Reg_En => Cont_Reg_En,
	Cont_MUX_Enable => Cont_MUX_Enable,
	Cont_MUX2_Enable =>  Cont_MUX2_Enable,
	--output
	Mux2_OUT => mux2_out_sig
	);

--Portmap registers
DCT_REG1:DCT_Reg  --register for output from DCT_Fofx
	PORT MAP (
		Clk => Clk,
		Reset => Reset,
		Reg_In => mux_out_sig,
		Reg_Out => reg1_out_sig,
		Reg_En => Reg_En
		);

DCT_REG2:DCT_Reg --register for DCT_cos
	PORT MAP (
		Clk => Clk,
		Reset => Reset,
		Reg_In => mux2_out_sig,
		Reg_Out => reg2_out_sig,
		Reg_En => Reg_En
		);

--Portmap of DCT_Calc
DCT_CALC_1: DCT_Calc
PORT MAP (
	Clk => Clk,			
	Reset => Reset,
	--Inputs to the Calculator unit
	fx => reg1_out_sig,
	Cos => reg2_out_sig,
	--Inputs from Controller
	Mult_Reg_En => Mult_Reg_En,
	Neg_Reg_En => Neg_Reg_En,
	Mult_Sel => Mult_Sel, 
	SOP_Reg_En => SOP_Reg_En,
	Output_Sel => Output_Sel,
	Clr_SOP_Reg => Clr_SOP_Reg,
	--Outputs of the Calculator Unit
	Negative => Negative,
	FofX => FofX
	);

end DCT_main_arch;