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University of Tennessee
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We propose to implement in field-programmable gate arrays (FPGAs) new encryption algorithms and key management to provide hardware acceleration for information security. We will work closely with ONR contractor(s) who have developed the mathematics of these algorithms. Thus, we will implement ONR-provided specifications to describe the desired functionality using the VHDL hardware description language and develop test-benches to verify proper operation via simulation. We will then use commercial electronic design automation (EDA) tools to synthesize the VHDL and to perform placement and routing and downloading into the FPGA device (e.g. Xilinx Virtex). We will then verify proper operation using post-layout simulation and physical measurement of the execution of the tasks on the FPGA device. Refinement of the above procedure will be performed to achieve efficient operation in terms of size, speed and power consumption. We will produce a report detailing both the development process and the implementation results.
The design flow we will follow is depicted in the figure below. An ONR contractor will supply C code with a testbench of stimuli and golden responses from executing the key management functions on a general-purpose processor (CPU --Pentium or PowerPC). The University of Tennessee design team will duplicate these on its own system and then manually covert the C code to the VHDL hardware description language and then implement the design on a FPGA (Virtex or VirtexII-Pro). Identical results should be obtained to verify that the FPGA implementation matches the desired specifications. The latencies (Delta-1 and Delta-2) of the two implementations will be recorded to determine the acceleration provided by the FPGA as compared to the Pentium.
A PRELIMINARY demonstration of both the Pentium and Virtex executions will be performed during the summer of 2003 and optimization of the FPGA implementation will be deferred until a subsequent period.
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